Rev. 4146JAERO06/03

Features

Fast Access Time: 30/45 ns

Wide Temperature Range: -55

C to +125

Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility

Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
More Than One Device

On-chip Arbitration Logic

Versatile Pin Select for Master or Slave:

M/S = H for Busy Output Flag On Master
M/S = L for Busy Input Flag On Slave

INT Flag for Port to Port Communication

Full Hardware Support of Semaphore Signaling Between Ports

Fully Asynchronous Operation From Either Port

Battery Back-up Operation: 2V Data Retention

TTL Compatible

Single 5V + 10% Power Supply

QML Q and V with SMD 5962-91617

Introduction

The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit

16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as

a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.

Master and slave devices provide two independent ports with separate control,
address and I/O pins that permit independent, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
power mode.

Using an array of eight transistors (8T) memory cell, the M67025E combines an
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 5 µW.

For military/space applications that demand superior levels of performance and reli-
ability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.

Rad. Tolerant
High Speed
8 Kb x 16
Dual Port RAM

M67025E

M67025E

4146JAERO06/03

Functional Description

The M67025E has two ports with separate control, address and I/O pins that permit
independent read/write access to any memory location. These devices have an auto-
matic power-down feature controlled by CS. CS controls on-chip power-down circuitry
which causes the port concerned to go into stand-by mode when not selected (CS high).
When a port is selected access to the full memory array is permitted. Each port has its
own Output Enable control (OE). In read mode, the port's OE turns the Output drivers on
when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1.

The interrupt flag (INT) allows communication between ports or systems. If the user
chooses to use the interrupt function, a memory location (mail box or message center) is
assigned to each port. The left port interrupt flag (INT

) is set when the right port writes

to memory location 1FFE (HEX). The left port clears the interrupt by reading address
location 1FFE. Similarly, the right port interrupt flag (INT

) is set when the left port writes

to memory location 1FFF (HEX), and the right port must read memory location 1FFF in
order to clear the interrupt flag (INT

). The 16-bit message at 1FFE or 1FFF is user-

defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not
reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt
function.

Arbitration Logic

The arbitration logic will resolve an address match or a chip select match down to a min-
imum of 5 ns determine which port has access. In all cases, an active BUSY flag will be
set for the inhibited port.

The BUSY flags are required when both ports attempt to access the same location
simultaneously. Should this conflict arise, on-chip arbitration logic will determine which
port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that
allow the processor to hold the operation with its associated address and data. It should
be noted that the operation is invalid for the port for which BUSY is set LOW. The inhib-
ited port will be given access when BUSY goes inactive.

A conflict will occur when both left and right ports are active and the two addresses coin-
cide. The on-chip arbitration determines access in these circumstances. Two modes of
arbitration are provided: (1) if the addresses match and are valid before CS on-chip con-
trol logic arbitrates between CS

and CS

for access; or (2) if the CS are low before an

address match, on-chip control logic arbitrates between the left and right addresses for
access (refer to Table 4). The inhibited port's BUSY flag is set and will reset when the
port granted access completes its operation in both arbitration modes.

Data Bus Width
Expansion

Expanding the data bus width to 32 or more bits in a dual-port RAM system means that
several chips may be active simultaneously. If every chips has a hardware arbitrator,
and the addresses for each arrive at the same time one chip may activate in L BUSY
signal while another activates its R BUSY signal. Both sides are now busy and the
CPUs will wait indefinitely for their port to become free.

To overcome this "Busy Lock-Out' problem, Atmel has developed a MASTER/SLAVE
system which uses a single hardware arbitrator located on the MASTER. The SLAVE has
BUSY inputs which allow direct interface to the MASTER with no external components, giving a
speed advantage over other systems.

When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented
from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a conflict situation. Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is
inherent in all dual-port memory systems where more than one chip is active at the same time.

M67025E

4146JAERO06/03

The write pulse to the SLAVE must be inhibited by the MASTER's maximum arbitration
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER's BUSY signal.

Semaphore Logic

The M67025E is an extremely fast dual-port 4 Kb

16 CMOS static RAM with an additional

locations dedicated to binary semaphore flags. These flags allow either of the processors on the
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by one processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.

The dual-port RAM has a fast access time, and the two ports are completely indepen-
dent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict aris-
ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-
semaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in Table 1 where CS and SEM are both high.

Systems best able to exploit the M67025E are based around multiple processors or con-
trollers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.

Software handshaking between processors offers the maximum level of system flexibil-
ity by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more usual methods of hardware
arbitration is that neither processor ever incurs wait states. This can prove to be a con-
siderable advantage in very high speed systems.

How The Semaphore
Flags Work

The semaphore logic is a set of eight latches independent of the dual-port RAM. These
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provides the hardware context for the "Token
Passing Allocation' method of use assignment. This method uses the state of a sema-
phore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left proces-
sor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the sta-
tus of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.

The semaphore flags are active low. A token is requested by writing a zero to a sema-
phore latch, and is relinquished again when the same side writes a one to the latch.

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 5962-9161706VZC