1
Features
Atmel Advanced System Bus (ASB) Arbitration
Customized Options
Number of Masters (2 to 7)
Priority of Masters
Possibility of Inserting Master Hand-over Cycle for Each Master
Atmel AMBA
TM
Master Compliant
Fully Scan Testable up to 96% Fault Coverage
Description
The Advanced System Bus (ASB), part of the Advanced Microcontroller Bus Architec-
ture (AMBA), supports the connection of multiple processors. Therefore, it requires an
arbiter to ensure that only one bus master has write access to the ASB at any particu-
lar point in time. Each bus master can request the bus; the Arbiter decides which
master has the highest priority and issues a grant accordingly. A hand-over cycle is
inserted if required.
Each master is connected to the Arbiter via two signals:
A request signal areq: output from the master, input to the arbiter
A grant signal agnt: input to the master, output from the arbiter
For further information on the AMBA structure, Master Signals Manager and Read
Data Manager, refer to the ARM7TDMI
TM
System Architecture datasheet, Literature
Number 1353.
Figure 1. Arbiter Symbol
Scan Test Configuration
The coverage is maximum if all non-scan inputs can be controlled and all non-scan
outputs can be observed. In order to achieve this, the ATPG vectors must be gener-
ated on the entire circuit (top level) which includes the Arbiter or all Arbiter I/Os must
have a top-level access and ATPG vectors must be applied to these pins.
scan_test_mode
Arbiter
AMBA Bus
Inputs
agnt[N-1:0]
blok[N-1:0]
nreset_f
areq[N-1:0]
nclock
AMBA Bus
Output
Scan Test
test_si
test_se
test_so
32-bit
Embedded Core
Peripheral
Arbiter
Rev. 1284D03/01
2
Arbiter
1284D03/01
Notes:
1. N = Number of masters
2. The scan chain uses the clock nclock.
Table 1. Pin Description
Name
Type
Source/Destination
Description
AMBA Bus Inputs
nreset_f
Input
From Reset Controller
System reset for parts synchronized on the falling edge of the ASB
clock (nclock). Active low.
nclock
Input
ASB system clock.
blok[N
(1)
-1:0]
Input
From Masters
Locked transfers. Active high.
areq[N
(1)
-1:0]
Input
From Masters
Bus request. Each master has a corresponding areq signal. Active
high.
agnt[N
(1)
-1:0]
Output
To Masters
Bus grant. Each master has a corresponding agnt signal. Active
high.
Scan Test
scan_test_mode
Input
For scan test only. This input must be set to 1 only during scan test.
Must be set to 0 in normal operating mode.
test_se
Input
Test scan shift enabled when tied to 1.
test_si
(2)
Input
Test scan input (input of the scan chain).
test_so
(2)
Output
Test scan output (output of the scan chain).
3
Arbiter
1284D03/01
Operating in an
AMBA System
Figure 2. AMBA Data Buses
brdata
BD_from_masters
BD_from_APB
BDout
ARM Memory
Controller
(including Decoder,
EBI and ARAM
Controller)
bwait_from_APB
bwait_to_ASB
wait_1C
data_to_master
pdc_data
data_from_masters
APB
Peripherals
Bridge
areq
agnt
bwait_in
bwdata
Arbiter
(N masters)
agnt[N-1]
areq[N-1]
pdc_sel_bridge
ARM7TDMI
Core and Wrapper
bridge_sel
Advanced System
Bus (ASB)
Advanced Peripheral
Bus (APB)
dsel_bridge
Read
Data
Manager
Master
Signals
Manager
agnt[i]
areq[i]
bwait_in
bwdata
brdata
agnt
areq
Master[i]
(DOUT on
ARM Core)
(DIN on
ARM Core)
4
Arbiter
1284D03/01
Figure 3. Master Control Signals
blok
bprot
bsize
btran
btran[1:0]
ARM Memory
Controller
(including Decoder,
EBI and ARAM
Controller)
ba
write_
master
address
APB
Peripherals
Bridge
blok[N-1:0]
Arbiter
(N masters)
agnt[N-1]
areq[N-1]
bwrite
agnt[i]
areq[i]
agnt
areq
Master
mabe
ba
bprot_(N-1)
bsize_(N-1)
btran_(N-1)
BusEnable_(N-1)
ba_(N-1)
bwrite_(N-1)
bwrite
bsize
bprot
blok
ba
bwrite
btran
BusEnable
agnt[N-1]
agnt[i]
bsizeout
bprotout
baout
bwriteout
btranout
Master
Signals
Manager
not used in
this configuration
bprot_(i)
bsize_(i)
btran_(i)
BusEnable_(i)
ba_(i)
bwrite_(i)
bsize
2
2
2
2
2
2
2
2
agnt[N-1]
ARM7TDMI
Core and Wrapper
areq[N-1]
5
Arbiter
1284D03/01
Functional
Description
The configuration described below is an example in which the arbiter manages six masters.
The waveforms which follow use the same configuration.
The arbitration scheme of this implementation is a simple priority encoded scheme where the
highest priority master requesting the ASB is granted.
Note:
The priority order is defined differently during reset.
Priority
In operational mode (reset inactive), the priority order is defined Table 2 from the highest prior-
ity to the lowest priority. If no request is present, the default master is granted and is in charge
of driving BTRAN to a valid value.
Note:
During reset (active low), only the default master can be granted control of the bus. Therefore,
whatever the value of areq, agnt[5:0] is 000001.
Note:
U takes the place of 0 or 1.
Table 2. Priority Level
Priority
Level
Connection
Example
of Master
1
areq[0] and agnt[0]
Default master
2
areq[1] and agnt[1]
Debug
3
areq[2] and agnt[2]
DMA
4
areq[3] and agnt[3]
PDC
5
areq[4] and agnt[4]
Coprocessor core
6
areq[5] and agnt[5]
ARM
Core
Table 3. Arbitration Examples
Request
Granted Response
areq[5:0] = UUUUU1
agnt [5:0] = 000001
areq[5:0] = UUUU10
agnt [5:0] = 000010
areq[5:0] = UUU100
agnt [5:0] = 000100
areq[5:0] = UU1000
agnt [5:0] = 001000
areq[5:0] = U10000
agnt [5:0] = 010000
areq[5:0] = 100000
agnt [5:0] = 100000
areq[5:0] = 000000
agnt [5:0] = 000001
Therefore:
areq[5:0] = 000101
agnt [5:0] = 000001
areq[5:0] = 011101
agnt [5:0] = 000001
areq[5:0] = 111110
agnt [5:0] = 000010
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