1
Features
Serial EEPROM Family for Configuring Altera FLEX
Devices
In-System Programmable via 2-wire Bus
Simple Interface to SRAM FPGAs
EE Programmable 64K, 128K and 256K bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future Higher-density
Arrays (128K and 256K only)
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package (Compatible Across
Product Family)
Emulation of Atmel's AT24CXXX Serial EEPROMs
Available in 3.3V 10% LV and 5V 5% C Versions
Description
The AT17C65A/128A/256A and AT17LV65A/128A/256A (low-density AT17A Series)
FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective
configuration memory for programming Altera FLEX
devices. The AT17A series is
packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-
access procedure to configure one or more FPGA devices. The AT17A series organi-
zation supplies enough memory to configure one or multiple smaller FPGAs. Using a
feature of the AT17A series, the user can select the polarity of the reset function by
programming a special EEPROM byte. These devices also support a write protection
mechanism within its programming mode.
The AT17A Series Configurators can be programmed with industry standard program-
mers, or Atmel's ATDH2200E Programming Kit.
Pin Configurations
PLCC
Note:
1. To order the 8-lead PDIP version refer to "FPGA Configuration EEPROM: 65K,
128K, and 256K" (doc #0391).
4
5
6
7
8
18
17
16
15
14
DCLK
NC
NC
NC
(WP) OE
SER_EN
NC
NC
NC
NC
3
2
1
20
19
9
10
11
12
13
nCS
GND
NC
(A2) nCASC
NC
NC
DATA
NC
VCC
NC
FPGA
Configuration
EEPROM
Memory
64K, 128K and 256K
Altera Pinout
AT17C65A
AT17LV65A
AT17C128A
AT17LV128A
AT17C256A
AT17LV256A
Rev. 0996B10/99
AT17C/LV65A/128A/256A
2
Block Diagram
Device Configuration
The control signals for the configuration EEPROM--nCS,
OE, and DCLK--interface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
controller.
The configuration EEPROM device's OE and nCS pins
together control the tri-state buffer on the DATA output pin
and enable the address counter. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is subsequently
driven Low, the counter and the DATA output pin are
enabled. When OE is driven Low again, the address
counter is reset and the DATA output pin is tri-stated,
regardless of the state of nCS.
When the Configurator has driven out all of its data and
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
This document discusses the EPF8K and EPF10K device
interfaces. For more details or information on other Altera
applications, please reference the "AT17A Series Conver-
sions from Altera FPGA Serial Configuration Memories"
application note.
FPGA Device Configuration
FPGA devices can be configured with a low-density AT17A
Series EEPROM (Figure 1). The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially according to an external clock source.
The OE, nCS, and DCLK pins supply the control signals for
the address counter and the output tri-state buffer. The
AT17A Series device sends a serial bitstream of configura-
tion data to its DATA pin, which is connected to the DATA0
input pin on the FPGA device.
When configuration data for an FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascaded EEPROMs.
Note:
A single AT17C/LV65A may only be used at the end of a
cascade chain or as a standalone device.
DCLK
OE
nCS
nCASC
DATA
POWER ON
RESET
AT17C/LV65A/128A/256A
3
The first AT17A Series Configurator (whose nCS input is
directly driven by the FPGA) provides the first stream of
data to the FPGA device during multi-device configuration.
Once the first AT17A Series device finishes sending config-
uration data, it drives its nCASC pin Low, which drives the
nCS pin of the second AT17A Series device Low. This
allows the second AT17A Series device to send configura-
tion data to the FPGA.
If the nCS pin on the first AT17A Series device is driven
High before all configuration data is transferred--or if nCS
is not driven High after all configuration data is trans-
ferred--nSTATUS is driven Low, indicating a configuration
error.
The low density AT17A Series Configuration EEPROMs
are not designed to act as system masters (i.e. provide
clock pulses on the serial bus to other devices). Clocking
must be supplied by an FPGA device, a high-density
AT17A Series device (Figure 2), or an external oscillator.
Figure 1. FPGA device configured with a single AT17A Series Configurator.
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Reset polarity must be set active Low.
Figure 2. FPGA device configured with multiple AT17A Series Configurators.
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Reset polarity must be set active Low.
3. RC filter recommended for input to nCONFIG to delay configuration (100 ms to 200 ms) until V
CC
is stable within its normal
operating range. (nCONFIG can instead be connected to an active Low system reset signal).
4. Use of the READY pin is optional.
nCONFIG
nS/P
MSEL0
MSEL1
DCLK
DATA0
CONF_DONE
nSTATUS
DCLK
DATA
nCS
OE
AT17C65(A)/128(A)/256(A)
AT17LV65(A)/128(A)/256(A)
EPF8K
GND
VCC
VCC
VCC
VCC
nCONFIG
nS/P
MSEL0
MSEL1
DCLK
DATA0
CONF_DONE
nSTATUS
DCLK
DATA
nCS
OE
AT17C512A/010A
AT17LV512A/010A
Device 1
EPF10K
GND
GND
nCASC
READY
DCLK
DATA
nCS
OE
AT17C65(A)/128(A)/256(A)
AT17LV65(A)/128(A)/256(A)
Device 2
VCC
VCC
VCC
AT17C/LV65A/128A/256A
4
AT17A Series Reset Polarity
The AT17 Series Configurator allows the user to program
t he p o l a r i t y o f t h e O E p i n as eit h e r R E S E T / O E o r
RESET/OE. This feature is supported by industry standard
programmer algorithms. For more details on programming
the EEPROMs reset polarity, please reference the "Pro-
gramming Specification for Atmel's FPGA Configuration
EEPROMs" application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the "Programming Specification for Atmel's Con-
f i g u r a t i o n E E P R O M " a p p l i c a t i o n n o t e f o r f u r t h e r
information. The AT17CxxxA parts are read/write at 5V
nominal. The AT17LVxxxA parts are read/write at 3.3V
nominal.
Standby Mode
The AT17C/LV65A/128A/256A enters a low-power standby
mode whenever nCS is asserted High. In this mode,
the configurator consumes less than 75 A of current
at 5.0V. The output remains in a high-impedance state
regardless of the state of the OE input.
AT17C/LV65A/128A/256A
5
Note:
1. To order the 8-lead PDIP version refer to "FPGA Configuration EEPROM Memory: 64K, 128K and 256K" (doc.# 0391).
Pin Configurations
20 PLCC
Pin
8 DIP
(1)
Pin
Name
I/O
Description
2
1
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
4
2
DCLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
8
3
OE
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic
level resets the address counter. A High logic level (with nCS Low) enables DATA and
permits the address counter to count. The logic polarity of OE is programmable and must
be set active High (RESET active Low) by the user during programming for Altera
applications.
WP
I
Write Protect (WP) input (when nCS is Low) during programming only (i.e., when
SER_EN is Low). When WP is Low, the entire memory can be written. When WP is
enabled (High), the lowest block of the memory cannot be written. This function is not
available during FPGA loading operations. Please refer to the "Programming
Specification" application note for more details.
9
4
nCS
I
Chip select input (active Low). A Low input (with OE active) allows DCLK to increment
the address counter and enables DATA to drive out. A High level on nCS disables both
the address and bit counters and forces the device into a low-power standby mode. Note
that this pin will not enable/disable the device in the 2-wire Serial Programming Mode
(i.e., when SER_EN is Low).
10
5
GND
Ground pin. A 0.2 F decoupling capacitor should be placed between the VCC and
GND pins.
12
6
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of
one device must be connected to the nCS input pin of the next device in the chain. It will
stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes
Low, thereafter, nCASC will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e., when SER_EN is Low; please refer to the "Programming
Specification" application note for more details).
18
7
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
20
8
VCC
+3.3V/+5V Power Supply Pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125 C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature ..................................... -65 C to +150C
Voltage on Any Pin
with Respect to Ground .............................. -0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF)................................. 2000V
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