Features

Fast Read Access Time 70 ns

5-volt Only Reprogramming

Page Program Operation

Single Cycle Reprogram (Erase and Program)
Internal Address and Data Latches for 64 Bytes

Internal Program Control and Timer

Hardware and Software Data Protection

Fast Program Cycle Times

Page (64 Byte) Program Time 10 ms
Chip Erase Time 10 ms

DATA Polling for End of Program Detection

Low-power Dissipation

50 mA Active Current
300

µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

Single 5V

± 10% Supply

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges

Description

The AT29C256 is a five-volt-only in-system Flash programmable and erasable read
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.

256K (32K x 8)
5-volt Only
Flash Memory

AT29C256

Rev. 0046PFLASH10/04

PLCC and LCC Top View

Note:

PLCC package pins 1 and 17 are
DON'T CONNECT.

Pin Configurations

Pin Name

Function

A0 - A14

Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O7

Data Inputs/Outputs

No Connect

Don't Connect

I/O0

A11

A10

I/O7

I/O6

I/O1

I/O2

GND

I/O3

I/O4

I/O5

A12

VCC

A14

A13

TSOP Top View

Type 1

A11

A13

A14

VCC

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

AT29C256

0046PFLASH10/04

To allow for simple in-system reprogrammability, the AT29C256 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro-
gramming is not needed).

During a reprogram cycle, the address locations and 64 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected a new
access for a read, program or chip erase can begin.

Block Diagram

Device Operation

READ:

The AT29C256 is accessed like a static RAM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.

BYTE LOAD:

A byte load is performed by applying a low pulse on the WE or CE input

with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the
software codes for data protection and chip erasure.

AT29C256

0046PFLASH10/04

PROGRAM:

The device is reprogrammed on a page basis. If a byte of data within a

page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro-
grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-
high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 µs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of t

, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION:

A software controlled data protection feature is

available on the AT29C256. Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command
sequence is issued.

After setting SDP, any attempt to write to the device without the three-byte command
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of t

, a read operation will effectively be a polling operation.

After the software data protection's three-byte command code is given, a byte load is
performed by applying a low pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent

programs to the AT29C256 in the following ways: (a) V

sense if V

is below 3.8V

(typical), the program function is inhibited; (b) V

power on delay once V

has

reached the V

sense level, the device will automatically time out 5 ms (typical) before

programming; (c) Program inhibit holding any one of OE low, CE high or WE high
inhibits program cycles; and (d) Noise filter pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.

AT29C256

0046PFLASH10/04

PRODUCT IDENTIFICATION:

The product identification mode identifies the device

and manufacturer and may be accessed by a hardware operation. For details, see
Operating Modes or Product Identification.

DATA POLLING:

The AT29C256 features DATA polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte loaded will result
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.

TOGGLE BIT:

In addition to DATA polling the AT29C256 provides another method for

determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
cycle.

OPTIONAL CHIP ERASE MODE:

The entire device can be erased by using a six-byte

software code. Please see Software Chip Erase application note for details.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55

°C to +125°C

*NOTICE:

Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.

Storage Temperature ..................................... -65

°C to +150°C

All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages
with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

AT29C256

0046PFLASH10/04

Notes:

1. X can be V

or V

2. Refer to AC Programming Waveforms.
3. V

= 12.0V

0.5V.

4. Manufacturer Code: 1F, Device Code: DC.
5. See details under Software Product Identification Entry/Exit.

DC and AC Operating Range

AT29C256-70

AT29C256-90

AT29C256-12

AT29C256-15

Operating
Temperature (Case)

Com.

0°C - 70°C

Ind.

-40°C - 85°C

Power Supply

± 5%

± 10%

Note:

Not recommended for New Designs.

Operating Modes

Mode

I/O

Read

OUT

Program

(2)

5V Chip Erase

Standby/Write Inhibit

(1)

High Z

Write Inhibit

Output Disable

High Z

High Voltage Chip Erase

(3)

High

Product Identification

Hardware

A1-A14 = V

, A9 = V

, A0 = V

Manufacturer Code

(4)

A1-A14 = V

, A9 = V

, A0 = V

Device Code

(4)

Software

(5)

A0 = V

Manufacturer Code

(4)

A0 = V

Device Code

(4)

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

Input Load Current

= 0V to V

µA

Output Leakage Current

I/O

= 0V to V

µA

SB1

Standby Current CMOS

CE = V

- 0.3V to V

300

µA

SB2

Standby Current TTL

CE = 2.0V to V

Active Current

f = 5 MHz; I

OUT

= 0 mA

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

= 2.1 mA

0.45

OH1

Output High Voltage

= -400 µA

2.4

OH2

Output High Voltage CMOS

= -100 µA; V

= 4.5V

4.2

Document Outline

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Document Outline

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