1
Features
Prototype Board
PC/AT-Compatible Expansion Board Edge Connector
84-pin PLCC High-Pressure Tin Socket with Solder Tails
132-pin PQFP Micro Pitch Socket
Over 16 Square Inches of Wire Wrap Area
Test Point Headers for Easy Access to V
CC
, GND, and FPGA I/O Signals
Pre-Wired Header for Download Cable Connection
Pre-Wired Sockets for Serial EEPROM or Parallel Configuration EPROMs
Materials for Device Configuration via PC Parallel Port
Cable Adapter Nodule
DB25-Male-to-DB25-Female Cable
Ten Conductor Ribbon Cable
Description
Atmel's Prototype Kit lets engineers try out an FPGA design in silicon and analyze its
operation in a systems environment. The kit includes a PCB assembly with sockets for
two FPGAs and space for adding active components. The board can be set up to run
in at least three ways:
Attached to a host PC running the Atmel Integrated Development System. The
Design Manager control panel is used to send configuration data to the board via
the download cable supplied with the Integrated Development System.
Attached to a PC that isn't running the Atmel Integrated Development System. The
Integrated Development System generates download files that can be used on any
DOS-based PC to send configuration data to the board.
Not attached to a host PC (stand-alone). Sockets on the board are used to hold
EEPROMs programmed with configuration data. Power is supplied to the board
from an external source.
AT6000 Series Prototype Board
FPGA
Integrated
Development
System
Prototype Kit
AT6000
Rev. 0452D03/00
AT6000
2
Table 1. Board Contents (in alphabetical order)
Symbol
Name Description
C1-C12
Bypass Capacitors
Used to stabilize the V
CC
and GND lines and filter out unwanted frequency components.
Capacitors are placed near each FPGA to minimize and transient currents arising from device
switching and magnetic coupling. Bulk capacitors placed near power supply connections
accommodate the continually changing I
CC
requirements of the total power system.
D1
Power LED
Lights up when power is applied to the board.
E1, E3
AT27C010 Parallel
Eprom Socket
Holds standard 128K x 8 parallel EPROMs (e.g., Atmel AT27C010), which can be used with
configuration modes 1, 2, or 5. Table 3 lists recommended EPROMs. The configuration
application note (included with the "Integrated Development System") has more on
configuration modes.
E2, E4
Serial EEPROM Socket
Holds standard serial EEPROMs (e.g., Atmel AT17C128), which can be used with configuration
modes 3 or 4. Table 3 lists recommended EEPROMs. The configuration application note
(included with the "Integrated Development System") has more on configuration modes.
F1
Power Supply Fuse
(optional)
The board is wired with a zero
resistor which can be replaced with a solid-state fuse or
current-limiting device when such protection is desired.
J1
84-pin PLCC FPGA
Download Cable
Connector
Attaches the download cable to the board so a PC can be used to configure a 84-pin device
using mode 3.
J2
132-pin PQFP FPGA
Download Cable
Connector
Attaches the download cable to the board so a PC can be used to configure a 132-pin device
using mode 3.
J3, J4,
J5, J6
84-pin PLCC FPGA Pin
Access Headers
Provides access to all pins on a 84-pin PLCC FPGA. Pin access headers can be used for wire-
wrapping prototype circuits or for connecting the FPGA to a logic analyzer or oscilloscope. An
access header post is provided for each device pin, including power pins (refer to the AT6000
Series data sheet for device pin descriptions). The number next to each header post indicates
the header's corresponding package pin.
J7, J8,
J9, J10
132-pin PQFP FPGA
Pin Access Headers
Provides access to all pins on a 132-pin PQFP FPGA. Pin access headers can be used for
wire-wrapping prototype circuits or for connecting the FPGA to a logic analyzer or oscilloscope.
An access header post is provided for each device pin, including power pins (refer to the
AT6000 Series data sheet for device pin descriptions). The number next to each header post
indicates the header's corresponding package pin.
J11,
J12
Power Supply Access
Headers
Provides access to power and ground for wire wrapping circuits. Each power supply access
header shares a column of +5V pins, which in turn share power and ground with the FPGA,
EPROMs, configuration headers, and AT Bus edge connectors.
J13,
J14
AT Bus Access Headers
Provides access to the AT edge connector signals. Each AT bus access header is connected to
a finger. The power labels correspond to the bus standard. The GND and +5V edge connector
headers are already wired to the GND and +5V power planes on the prototype board.
J15
Power Supply
Connector
Connects a +5V supply to the prototype board when power is not supplied by a host PC. Two
connections are used for +5V, and two are used for GND. The fifth connection goes to an
unused board trace and can be wired for different applications. To attach a wire, depress the
lever, insert the wire into the hole, and release the lever to make solid contact with the wire.
Most gauges of stripped wire will work.
L0-L15
Ground Loops
Connects a logic analyzer or oscilloscope to the ground plan for cleaner, simpler test setup.
AT6000
3
Board Setup and Configuration Requirements
Attaching to a PC Running the Integrated
Development System
This setup lets the engineer configure devices from within
the Design Manager environment. There engineer doesn't
have to pull the FPGA out of the board or reprogram
EPROMs for each design iteration.
Figure 1. Ribbon Cable Header Connection 84-pin Socket
Board Setup
To link the board to a host PC, use the DB25-male-to-
DB25-female cable to connect the PC parallel or printer
port (LPT1: or LPT2:) to the cable adapter module. Use the
ten-conductor ribbon cable to connect the cable adapter
module to the configuration headers J1 and J2. Figure 1
and Figure 2 show how to connect the cable adapter mod-
ule to the 84-pin and 132-pin sockets respectively.
Bit streams sent over the PC parallel port use mode 3 (bit-
sequential, external CCLK see the AT6000 Series config-
uration application note for more information about configu-
ration modes). Make sure the FPGA is set up for mode 3
before applying power to the board.
To configure a device in the 84-pin socket, set mode switch
SW6 to 0, SW7 to 1, and SW8 to 1. This selects the correct
settings for mode 3 configuration: M2=0, M1=1, and M0=1.
Close the CS switch SW5 to supply a logical "0" to the CS
input.
To configure a device in the 132-pin socket, set mode
switch SW2 to 0, SW3 to 1, and SW4 to 1. This selects the
correct settings for the mode 3 configuration: M2=0, M1=1,
and M0=1. Close CS switch SW1 to supply a logical "0" to
the CS input.
It is very important that the PC and the prototype board
power supply be capable of sharing a common ground. The
download cable connects the PC parallel port ground to the
prototype board ground. The Schmitt trigger module gets
its power (~5mA) from the prototype board. The user is
responsible for solving any ground contention problems
between the PC and the user power supply. Atmel is not
responsible for damage to the PC or power supply caused
by improper grounding of the lab setup.
SW1-8
Mode Select Switches
SW8 M0 84-pin PLCC
SW7 M1 84-pin PLCC
SW6 M2 84-pin PLCC
SW5 CS 84-pin PLCC
SW4 M0 132-pin PQFP
SW3 M1 132-pin PQFP
SW2 M2 132-pin PQFP
SW1 CS 132-pin PQFP
Selects the configuration mode. Each switch is connected to one of the configuration control
pins (M0, M1, M2 or CS). When the switch is open, it drives the input with a logic "1". When
closed, it drives the input with a logic "0". The logical "1" and "0" positions are noted on the
board silkscreen.
U1
84-pin PLCC Socket
AMP Socket #821573-1
AMP Tool #821590-1
Holds any AT6000 Series device housed in an 84-pin PLCC package. The location of power,
ground, and configuration pins is constant throughout the family, making the socket compatible
with any AT6000 Series device in this package. The arrow on the socket indicated Pin 1. The
84-pin PLCC can be inserted by hand, but an extraction tool from AMP Incorporated (84 PLCC
#821590-1) can make removal easier.
U2
132-pin PQFP Socket
AMP Socket #821949-5
AMP Cover #821942-1
AMP Tool #821958-2
AMP Sheet #15-9516
Holds any AT6000 Series device housed in an 132-pin PLCC package. The location of power,
ground, and configuration pins is constant throughout the family, making the socket compatible
with any AT6000 Series device in this package. The arrow on the socket indicated Pin 1. An
insertion and extraction tool from AMP Incorporated (132 PQFP #821958-2) is recommended
for inserting and removing the PQFP.
Table 1. Board Contents (in alphabetical order) (Continued)
Symbol
Name Description
AT6000
4
Once the board is properly connected to the PC and the
mode switches are in their proper position, a power supply
of between 4.75 and 5.25 volts can be applied to jumper
J15. It is recommended that the supply be a minimum of 1
ampere to accommodate any current spikes generated by
high-speed, simultaneously switching outputs. If the power
LED does not light once power is supplied, immediately
disconnect power and check the polarity of hand-wired cir-
cuits and the power supply fuse for possible problems.
The prototype board can be treated like an add-in board
and put inside the PC chassis. Place the board inside the
PC and attach it to the PC/AT-compatible bus slot. Turn the
PC power supply off and do not use the power supply con-
nector J1 with this setup. The download cable should still
be connected to the parallel port and the prototype board in
the PC. Power is supplied from the PC bus.
Figure 2. Ribbon Cable Header Connecting 132-Pin Socket
Initiating Configuration
Instructions for using the "Design Manager" to generate the
bit stream appear in the "Integrated Development System
User's Guide". When generating the bit stream, make sure
of four things:
1.
The bit stream is generated using mode 3.
2.
Disable Data Check (B3) is not set or the CHECK
pin is tied high on the prototype board.
3.
The ERR pin is operating without interference so it
can verify the download process.
4.
LPT1: is the default printer port. To use LPT2:,
change the default setting in the "System
Setup/User Settings/Miscellaneous" panel.
Attaching to a PC that Isn't Running the
Integrated Development System
A security block restricts the "Integrated Development Sys-
tem" to a single PC, but an executable download program
(provided with the "Integrated Development System")
makes configuration more portable. Two files are used to
download configurations to the prototype board from any
PC/AT:
downld.exe
<design name>.bst
This setup is particularly useful if the test equipment
needed to analyze the design is in a different room or if
design work is divided among many engineers.
Board Setup
The prototype board connects to the host PC in the same
way as described in the previous section.
PC Setup
The following "Integrated Development System" files are
use to download a bit stream from the host PC:
downld.exe
Downld.exe transfers the .bst file from the PC to the
prototype board. It is stored with the other executables in
the \atmel\bin\ directory. It is the only executable file
needed by the host PC.
It uses the dual-function ERR pin to detect errors in
downloading the configuration file. If ERR goes low, an
error has occurred. The error is displayed on the screen.
To prevent false errors, make sure the ERR pin operates
without interference during the download process. Refer
to the AT6000 Series configuration application note for
more on dual-function pins.
<design name>.bst
Contains the bit stream used to configure the device.
The "Integrated Development System User's Guide"
describes how to generate a <design name>.bst file.
AT6000
5
Follow these steps to set up the host PC for downloading
configuration. Refer to the "Integrated Development
System User's Guide" for more details.
1.
Load the downld.exe file onto the PC.
2.
Load the <design name>.bst file onto the PC.
3.
Place the design.cfg file, edited to specify the paral-
lel port to be used (LPT1: is the default), in the
project sub-directory.
Initiating Configuration
Table 1 lists commands used to invoke the downld.exe
files. Port can be either of the parallel printer ports LPT1 or
LPT2. LPT1 is the default. The port argument is case-sen-
sitive.
Configuring as a Stand-Alone
(Not Attached to a Host PC)
It is possible to use the prototype board without the down-
load cable. The prototype board is supplied with sockets for
serial EEPROMs and parallel configuration EPROMs.
Stand-alone operation can be used to test and verify mem-
ory devices before production. It can also help in the verifi-
cation of a prototype system using auto configuration.
Mode 4 loads configuration data from the EEPROM right
after the application of power. Mode 5 does not automati-
cally generate a CON signal after the power-up boot
sequence. Configuration is initiated by driving CON low.
Serial EEPROMs are best suited for mode 4 configuration,
parallel EPROMs for mode 5.
Board Setup
Sockets E1 and E3 hold standard 128K-x-8 parallel
EPROMs (e.g., AT 27C010), which can be used with con-
figuration modes 1, 2, or 5. Figure 3 shows how the socket
is wired to the FPGA.
Sockets E2 and E4 hold standard serial EEPROMs (e.g.,
AT17128), which can be used with configuration modes 3
or 4. Figure 4 shows how the socket is wired to the FPGA.
The AT6000 Series configuration application note gives
more detailed configuration requirements. When setting up
the board for auto-configuration, make sure of three things:
1.
The configuration mode select switches are set to
the proper value before power is applied to the
board.
2.
The CS switch for the device being used is closed.
3.
If a mode other than 4 or 5 is to be used, a configu-
ration clock must be supplied by the user. Configu-
ration is initiated by pulsing the CON pin low.
In this setup, power is applied through the J15 jumper, or
the board is installed into a PC bus. Make sure the mode
switches are set and the programmed memory device is
properly installed before applying power to the host PC.
Figure 3. Parallel EPROM and Mode 5 Configuration
Figure 4. Serial EEPROM and Mode 4 Configuration
EEPROM Setup
The "Integrated Development System" can generate a bit
stream in the Intel HEX format, accepted by most program-
mers. To generate a bit stream in HEX format, run the "Bit
Stream" or "Cascade" program with the "Intel Hex Format"
box checked in the "Device Programming/Build Bit Stream"
panel or the "Device Programming/Bit Stream Utilities/Cas-
cade Bit Stream" panel, as appropriate.
See the "Integrated Development System User's Guide" for
more information.
A Note About EPROMs and EEPROMs
Virtually any EPROM with an access time faster than 500
ns and an active-low output enable control is suitable for
storing configuration data. FPGA density and required con-
Table 2. Commands Used to Invoke Download.exe Files
DOWNLD <design name>
DOWNLD /P LPT2 <design name>.bst
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