1
Features
8-bit Embedded Microcontroller Core Optimized for Control Applications
Microcode, Software-compatible with Industry-standard 8032 Devices:
Instruction Set: Arithmetic Operations, Logical Operations, Boolean Variable
Manipulation, Data Transfer, Program Branching
8032-standard Execution Timing
Harvard Architecture, Featuring Separate Program and Data Memories:
64K Bytes Program Memory Address Space (EEPROM or Flash Memory)
64K Bytes Data Memory Address Space (RAM or EEPROM)
256 Bytes of Internal Data RAM
32 Bi-directional and Individually Addressable I/O Port Pins
Three 16-bit Timer/Counters
Full Duplex UART
8-source/6-vector Interrupt Structure with Two Priority Levels
Full Scan and Memory BIST Implemented
99% Fault Coverage
Description
The AT_8032 is an 8-bit embedded microcontroller core based on a microcode that is
software-compatible (instruction set and execution timing) with industry-standard
8032 devices. It is manufactured using Atmel's high-density CMOS technology and is
ideal for medium-complexity embedded control functions and cost-sensitive
applications.
Figure 1. Symbol
Communication
Port
Clock Input
Enable
Control
SCAN
P0_i<7:0>
P3_i<7:0>
P2_i<7:0>
P1_i<7:0>
P0_o<7:0>
P3_o<7:0>
P2_o<7:0>
P1_o<7:0>
P0_en
P3_e<7:0>
P2_e<7:0>
P1_e<7:0>
TEST_SE
TEST_SI1
TEST_SI2
TEST_SI3
TEST_SI4
CLK
AT8032
BIST
BIST_TEST
BIST_CLK
BIST_RESULT
Miscellaneous
RESET
RESET_BSTPS
TEST
ALE
obs_uart
obs_int
obs_timer
PSEN
TEST_SO1
TEST_SO2
TEST_SO3
TEST_SO4
Embedded
Microcontroller
Core
AT_8032
Rev. 0875B03/00
AT_8032 Core
2
Architecture
Figure 2. Block Diagram of the AT_8032 Microprocessor Core
P0.0-P0.7
P2.0-P2.7
Port 0
Drivers
Port 2
Drivers
RAM Addr
Register
RAM
Port 0
Latch
Port 2
Latch
ROM
B Register
Accumulator
Stack
Pointer
Program
Address
Register
Buffer
PC
Incrementer
Program
Counter
Data
Pointer
Temporary
Register 2
Temporary
Register 1
ALU
Program
Status
Word
Timing and
Control
Instruction
Register
PSEN
ALE
RST
PD
Oscillator
XTAL1
XTAL2
Port 1
Latch
Port 1
Drivers
Port 3
Latch
Port 3
Drviers
P1.0-P1.7
P3.0-P3.7
Interrupt, Serial Port
and Timer Blocks
PCON
SCON
TMOD
TCON
TL0
TH1
TL1
TH2
RCAP2L
SBUF
IE
IP
T2CON
TH0
TL2
RCAP2H
AT_8032 Core
3
Memory Organization
The AT_8032 has a Harvard architecture with separate
program and data memories (both 64K address spaces). In
addition, there is an internal 384-byte data memory which
can be accessed by 8-bit addresses. This enables data to
be stored and manipulated more quickly.
Program memory is read-only. In the ROM version, the
lowest 4K, 8K or 16K bytes of program memory are pro-
vided on-chip. In the ROMless versions all program
memory is external. The Program Store Enable (signal
PSEN) is the read strobe for external program memory.
Data memory is in a separate address space from program
me mo ry. U p to 6 4K b yt es of exte rna l RAM c an b e
addressed in the external data memory space. The
AT_8032 produces read (RD) and write (WR) signals as
required.
Combination of the external program memory and the
external data memory is possible. In this case, it is neces-
sary to apply the RD and PSEN signals to the inputs of an
AND gate, and to use the output of the gate as the read
strobe to the external program/data memory.
Figure 3. Program Memory
0000
FFFF
64K Bytes
PSEN
Direct and Indirect
Addressing
External
Program Memory
Internal
Data Memory
Indirect Addressing
Only
80H
7FH
00H
FFH
Special Function Register
Direct Addressing
Only
128 bytes
128 bytes
80H
FFH
128 bytes
Read Only
Memory
AT_8032 Core
4
External Program Memory
16 I/O lines are dedicated to the bus for external program
m e m o r y f e t c h e s . P o r t 0 i s u s e d a s a m u l t i p l e x e d
address/data bus. It gives the low byte of the program
counter as an address and waits for the arrival of the code
byte from the program memory. During the time the low
byte of the program counter is available on P0, the ALE sig-
nal clocks this byte into an address latch. Meanwhile, Port
2 provides the high byte of the program counter. Then
PSEN strobes the program memory and the code byte is
read into Port 0.
Program memory addresses are always 16 bits wide even
if the program memory is less than 64K bytes.
Figure 4. Executing from External Program Memory
Program Memory - Reset and Interrupt
Handling
At reset, the AT_8032 microcontroller executes from pro-
gram address 0000H.
The program memory has fixed 8-byte locations for 8 inter-
rupt service routines. Each interrupt makes the AT_8032
jump directly to the corresponding location. When the
microcontroller is at this location, it begins the execution of
the interrupt service routine.
For example, External Interrupt 0 is assigned to location
0003H. If External Interrupt 0 is going to be used, its ser-
vice routine must be at location 0003H. If not used, this
location can be used as part of the general purpose pro-
gram memory.
If an interrupt service routine is short enough, it can reside
entirely within its 8-byte interval. Longer service routines
can use a jump instruction to skip over subsequent inter-
rupt locations if other interrupts are in use.
Figure 5. Map of the Lower Part of the Program Memory
PSEN
P2
ALE
EA
P0
8032
ADDR
OE
D
Q
Latch
P1
P3
ROM
Reset
Interrupt
Locations
0000H
0003H
000BH
0013H
001BH
0023H
8 Bytes
AT_8032 Core
5
External Data Memory
The AT_8032 can be configured to interface with an exter-
nal data memory of up to 64K Bytes or 16-bit words. One-
byte addresses are generally used in conjunction with one
(or more) I/O lines to page the RAM. If the entire 64K
address space is to be accessed, two-byte addresses are
used.
Figure 6 represents a hardware configuration that allows
access to 2K bytes of external RAM. In this case, the
AT_8032 executes from the internal ROM. Port 0 functions
as multiplexed address/data bus to the RAM, and 3 lines of
Port 2 are used to page the RAM. The AT_8032 generates
RD and WR signals as required during external RAM
access.
Figure 6. Accessing External Data Memory
Internal Data Memory
The internal data memory is divided into three different
areas: one for the lower 128 bytes, one for the upper 128
bytes and the third 128 bytes for the Special Function Reg-
ister (SFR) space.
Internal data memory addresses are always 1 byte wide
(the address space is only 256 bytes). This is increased to
384 bytes by the following mechanism: direct addresses
higher than 7FH access one memory space (the SFRs),
but indirect addresses higher than 7FH access a different
memory space. The address space from 00H to 7FH can
be accessed by both direct and indirect addressing.
Lower 128 Bytes of Internal RAM
The lower 128 bytes of internal RAM can be addressed by
direct or by indirect addressing.
The lowest 32 bytes of the internal RAM are grouped into 4
banks of 8 registers. Program instructions refer to the regis-
ters as R0 through R7. Two bits in the Program Status
Word choose the register bank that is to be used. Because
register instructions are shorter than instructions that use
d ire c t a dd res s e s , th e c o de s pa c es a re u s ed m o re
efficiently.
Figure 7. The Lower 128 Bytes of Internal RAM
P2
8032
ALE
P0
ADDR
OE
PS
WE
WR
RD
DATA RAM
Page
Bits
D
Q
Latch
I/O
7FH
2FH
1FH
17H
0FH
07H
0
08H
10H
18H
20H
00
01
10
11
Stack Pointer
Reset Value
Bit-Addressable Space
(Bit Address 00H-7FH)
Bank Select
Bits in PSW
30H
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