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Электронный компонент: e1467D

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e1467D
Rev. A2, 15-Jan-01
1 (6)
32-kHz Clock CMOS IC with Digital Trimming and Alarm
Features
D 32-kHz voltage regulated oscillator
D 1.1 V to 2.2 V operating-voltage range
D Integrated capacitors for digital trimming
D Suitable for up to 12.5 pF quartz
D Trimming inputs insensitive to stray capacitance
D Output pulse formers
D Mask options for motor period and pulse width
D Low resistance output for bipolar stepping motor
D Alarm function
D Motor-fast-test function
Pad Configuration
VDD
*
V
SS
2
8
6
5
7
e 1467D
1
9
13
12
11
10
4
3
**ALIN /
**MOT1L
OSCIN
OSCOUT
ALOUT
MOT2
MOT1R
*
SC4 SC3 SC2 SC1
MTEST
9611897
*) The pads for V
DD
and OSCOUT are interchangeable
per mask option
**) The pads for ALIN/-MTEST and MOT1L are inter-
changeable per mask-option
Figure 4. Pad configuration
General Description
The e1467D is an integrated circuit in CMOS Silicon
Gate Technology for analog clocks. It consists of a
32-kHz oscillator, frequency divider, output pulse
formers, push-pull motor drivers and alarm output.
Integrated capacitors are mask-selectable to accomodate
the external quartz crystal. Additional capacitance can be
selected through pad bonding for trimming the oscillator
frequency.
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Supply voltage
V
SS
0.3 to 5 V
V
Input voltage range, all inputs
V
IN
(V
SS
0.3 V)
x V
IN
x (V
DD
+ 0.3 V)
V
Output short circuit duration
indefinite
Power dissipation (DIL package)
P
tot
125 mW
mW
Operating ambient temperature range
T
amb
20 to +70
C
Storage temperature range
T
stg
40 to + 125
C
Lead temperature during soldering at 2 mm
distance, 10 seconds
T
sld
260
C
Absolute maximum ratings define parameter limits
which, if exceeded, may permanently change or damage
the device.
All inputs and outputs in Atmel Wireless &
Microcontrollers' circuits are protected against
electrostatic discharges. However, precautions to
minimize the build-up of electrostatic charges during
handling are recommended.
This circuit is protected against supply voltage reversal
for typically 5 minutes.
e1467D
Rev. A2, 15-Jan-01
2 (6)
Functional Description
Oscillator
An oscillator inverter with feedback resistor is provided
for generation of the 32768 Hz clock frequency. Values
for the fixed capacitors at OSCIN and OSCOUT are
mask-selectable (see note 3 of operating characteristics).
Four control inputs SC1 to SC4 enable the addition of
integrated trimming capacitors to OSCIN and OSCOUT,
providing 15 tuning steps.
Trimming Capacitors
A frequency variation of typ. 4 ppm for each tuning step
is obtained by bonding the capacitor switch pads to V
DD
.
As none of these pads are bonded, the IC is in an
untrimmed state. Figure 5 shows the trimming curve
characteristic.
Note:
For applications which utilize this integrated trimming
feature, Atmel Wireless & Microcontrollers will deter-
mine optimum values for the integrated capacitors
C
OSCIN
and C
OSCOUT.
Motor Drive Output
The e1467D contains two push-pull output buffers for
driving bipolar stepping motors. During a motor pulse,
the n-channel device of one buffer and the p-channel
device of the other buffer will be activated. Both
n-channel transistor are on and conducting, between
output pulses. The outputs are protected against inductive
voltage spikes with diodes to both supply pins. The motor
output period and pulse width are mask programmable, as
listed below:
Available motor periods (T
M
):
125, 250, 500 ms and 2, 16 s
Available max. pulse widths (t
M
):
15, 6, 23.4, 31.25, 46.9 ms
Available motor periods for motor test (T
MT
):
250, 500 ms and 1 s
Note: The following constraints for combination of
motor period and pulse widths have to be
considered: T
M
u
4 *
t
M
, T
MT
u
4 *
t
M
or
alternatively T
M
= 2 * t
M
, T
MT
= 2 * t
M
Alarm Outputs
The alarm output driver consists of push-pull stage for
driving a speaker via an external bipolar transistor.
The output is configured for npn and pnp bipolar
capability. The output is an alarm tone modulated by a
low frequency. Tone frequencies, modulation
frequencies, and on/off times are selectable via the metal
mask option.
Alarm Input
A debounced alarm input is provided. Alarm activation is
either to V
DD
or V
SS
by a mask option.
Test Functions
For test purposes the ALIN/MTEST pad is open. With a
high resistance probe (R
w 10 MW, C v 20 pF), a test
frequency f
TEST
of 128 Hz can be measured at the ALIN/
MTEST pad. Connecting ALIN/MTEST (for at least
32 ms) to the opposite polarity for alarm activation
changes the motor period from the selected value to T
MT
(mask-selectable) while the pulse width remains
unaffected. This feature can be used for testing the
mechanical parts of the clock.
SC4
SC3
SC2
SC1
e1467D
MOT1L
ALIN/
OSCIN
OSCOUT
ALOUT
MOT2
MOT1R
R3
R2
V
DD
V
SS
R1
1
2
3
4
5
6
7
8
9
10
11
12
13
V
SS
V
DD
MT
9611896
Figure 5. Functional test
Test Crystal Specification
Oscillation frequency
f
OSC
= 32768 Hz
Series resistance
R
S
= 30 k
W
Static capacitance
C
O
= 1.5 pF
Dynamic capacitance
C
1
= 3.0 fF
Load capacitance
C
L
optionally 10 or 12.5 pF
e1467D
Rev. A2, 15-Jan-01
3 (6)
Operating Characteristics
V
SS
= 0, V
DD
= 1.5 V, T
amb
= +25
C, unless otherwise specified
All voltage levels are measured with reference to V
SS
. Test crystal as specified below.
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Operating voltage
V
DD
1.1
1.5
2.2
V
Operating temperature
T
amb
20
+70
C
Operating current
R
1
=
, note 2
I
DD
1
3
mA
Motor drive output
Motor output current
V
DD
= 1.2 V, R
1
=
200
W
I
M
"4.3
mA
Motor period
T
M
See option list
s
Motor period during motor
test
T
MT
See option list
ms
Motor pulse width
t
M
See option list
ms
Oscillator
Startup voltage
Within 2 s
V
START
1.2
2.2
V
Frequency stability
DV
DD
= 100 mV
V
DD
= 1.1 to 2.2 V
Df/f
0.1
0.2
ppm
Integrated input capacitance
Note 3
C
OSCIN
See option list
pF
Integrated output capacitance
C
OSCOUT
See option list
pF
Input current SC1 to SC4
V
IN
= 0.2 V
V
IN
= V
DD
, note 5
I
SCINL
I
SCINH
1
0.05
5
0.15
25
0.5
mA
mA
Alarm/output
Output current for
driving npn-transistor
V
DD
= 1.2 V
n-channel
R
3
= 100 k
W
I
ANn
1
3
10
mA
p-channel
R
2
= 1 k
W, note 2, note 4
I
ANp
0.5
1
mA
Output current for
driving pnp-transistor
V
DD
= 1.2 V
n-channel
R
3
= 1 k
W
I
APn
0.5
1
mA
p-channel
R
2
= 100 k
W, note 2, note 4
I
APp
1
2
10
mA
Alarm options
Tone frequency
f
A
See option list
Hz
Modulation frequency
f
MOD
See option list
Hz
On/Off time
t
ON
/t
OFF
See option list
s
Alarm input/motor test
Input current
ALIN = V
DD
, peak current
I
AINH
0.6
3
10
mA
Input current
ALIN = V
SS
, peak current
I
AINL
0.6
3
10
mA
Input debounce delay
t
AIN
23.4
31.2
ms
Note 1: Typical parameters represent the statistical mean values
Note 2: See test circuit
Note 3: Values can be selected in 1 pF steps. A total capacitance (C
OSCIN
+ C
OSCOUT
) of 38 pF is available
Note 4: npn or pnp driving transistors defined by mask options
Note 5: I
SCINH
is the peak current of a pulsed current with duty cycle 1:63. Average current is always smaller than
10 nA
e1467D
Rev. A2, 15-Jan-01
4 (6)
Motor output signal during normal mode and motortest
ALIN/
MT
MOT1
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
MOT2
t
M
T
M
T
MT
1/f
TEST
a
Detail a:
9611898
Figure 6. Motor output signal during normal operation and during motor test
1/f
A
1/f
MOD
V
DD
V
SS
Detail b:
Alarm output signal
t
ON
t
OFF
V
DD
V
SS
ALOUT
Signal on alarm input and alarm output during alarm activation
V
DD
V
SS
b
ALIN /
MTEST
T < t
AIN
T > t
AIN
T < t
V4
T > t
V4
9611899
Figure 7. Alarm operation
e1467D
Rev. A2, 15-Jan-01
5 (6)
1.99991
1.99992
1.99993
1.99994
1.99995
1.99996
1.99997
1.99998
1.99999
2.00000
2.00001
2.00002
2.00003
2.00004
2.00005
2.00006
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Motorperiod (s)
Trimming steps
C
OX
=
0.95
1.00
1.05
9611900
Figure 8. Typical trimming curve characteristic for T
M
of 2 s
C
OX
means frequency deviation due to production process variations.
Trimming inputs SC1 ... SC4 are binary weighted, i.e., SC1 ... SC4 = 0 corresponds to trimming step 0
SC1 ... SC4 = 1 corresponds to trimming step 15
LSB = SC1