1
Features
Low-noise Low Drop Out Voltage Regulator
Programmable at 2.8V or 2.9V Output Voltages
3V to 5.5V Supply Operation
30 mA Maximum Load Current
Power-down Mode Consumption Less Than 1 A
Macrocell for Integration into System-on-chip Products
More Than 70 dB (Typical) PSRR at 1 kHz
32 V
RMS
Output Noise
0.35 m CMOS Technology
Typical Application: Radio Section Supply in Mobile Terminals
Description
RE025 is a Low Drop Out (LDO) voltage regulator macrocell with programmable 2.8V
or 2.9V output voltages, rated for loads of up to 30 mA. It is designed to be integrated
with other analog cells, digital logic, microcontrollers, DSP cores and memory blocks
into system-on-chip products.
The circuit consists of a PMOS pass device, an error amplifier and a feedback resis-
tive network, sized to achieve the required closed loop gain. These blocks make up
the regulating loop. An over-current and short circuit protection circuit has been
included to limit the output current delivered by the regulator, thus avoiding destruction
in case of a short circuit.
An external reference voltage (bandgap voltage) is necessary for correct functionality.
The target reference voltage is 1.231V, delivered, for example, by BG019. Double
pads on the supply voltage V
BAT3A
/V
BAT3AA
and output voltage V
PLLA
/V
PLLAA
are used to
reduce the total output resistance. Current reference is generated inside the cell
through a circuit supplied by a 2.5V 0.1V regulated input voltage on V
SAUVC
. Remote
sense terminal V
PLLS
provides regulation at the load by connecting it to the output ter-
minal near a critical point to improve performance of the regulator (e.g., connecting
them at the package pin by double-bonding thus avoiding the bonding resistance influ-
ence). A ceramic capacitor of 2.2 F connected from V
PLLA
/V
PLLAA
to ground is needed
as external compensation.
Figure 1. Symbol
(1)
Note:
1. Pin names are written as they appear on the user screen when the symbol is
opened in the design tool environment.
vsauvc
vbg
on3
trimldo3
vpllc
vbat3a
vbat3aa
vplla
vpllaa
vplls
gnd3
Embedded ASIC
Macrocell:
Power
Management for
Mobile
Terminals (PM)
RE025
Programmable
2.8V or 2.9V
30 mA
Low-noise LDO
Voltage
Regulator
Rev. 2700B-PMGMT02/03
3
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700BPMGMT02/03
Absolute Maximum Ratings
*
Electrical Specifications
(1)
T
J
= -20
C to 125
C, V
BAT3A
/V
BAT3AA
= 3V to 5.5V unless otherwise specified, output capacitance = 2.2 F.
V
IN
.......................................................... -0.3V to 6.5V
*NOTICE:
Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Digital Signals......................................... -0.3V to 5.5V
Output Current..................................Internally Limited
Junction Temperature ..........................-40
C to 150
C
Table 1. Electrical Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
V
BAT3A
/V
BAT3AA
Operating Supply Voltage
3
5.5
V
V
SAUVC
Auxiliary Operating Supply
Voltage
2.4
2.5
2.6
V
T
J
Junction Temperature Range
-20
125
C
V
PLLA
/V
PLLAA
Output Voltage
TRIMLDO3 = 0
2.75
2.8
2.85
V
TRIMLDO3 = V
BAT3A
/V
BAT3AA
2.855
2.9
2.935
V
I
PLLA
/I
PLLAA
Output Current
30
mA
I
CC
Quiescent Current
Any condition
140
250
A
V
DC
Line Regulation @2.8V
I
PLLA
/I
PLLAA
= 30 mA
2
3
mV
V
TRAN
Transient Line Regulation @2.8V
I
PLLA
/I
PLLAA
= 30 mA
rise time = fall time = 5 s
2
3
mV
V
DC
Load Regulation @2.8V
10% - 90% of I
PLLA
/I
PLLAA
2
3
mV
V
TRAN
Transient Load Regulation @2.8V
10% - 90% of I
PLLA
/I
PLLAA
rise time = fall time = 5 s
2
10
mV
V
DC
Line Regulation @2.9V
I
PLLA
/I
PLLAA
= 30 mA
2
3
mV
V
TRAN
Transient Line Regulation @2.9V
I
PLLA
/I
PLLAA
= 30 mA
rise time = fall time = 5 s
2
6
mV
V
DC
Load Regulation @2.9V
10% - 90% of I
PLLA
/I
PLLAA
2
4
mV
V
TRAN
Transient Load Regulation @2.9V
10% - 90% of I
PLLA
/I
PLLAA
rise time = fall time = 5 s
3
13
mV
4
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700BPMGMT02/03
Notes:
1. Obtained by considering the parasitics of a TFBGA100 Package.
2. Obtained by using BG019 as reference voltage generator.
PSRR
Power Supply Rejection Ratio
at Full Load
V
BAT
= 3V
@100 Hz
-75
dB
@1 kHz
-75
dB
@20 kHz
-45
dB
@100 kHz
-35
dB
V
BAT
= 4.25V
@100 Hz
-75
dB
@1 kHz
-75
dB
@20 kHz
-55
dB
@100 kHz
-45
dB
V
BAT
= 5.5V
@100 Hz
-75
dB
@1 kHz
-75
dB
@20 kHz
-60
dB
@100 kHz
-45
dB
V
N
Output Noise
(2)
Bandwidth = 10 Hz to 100 kHz;
output current = 30 mA
32
50
V
RMS
T
R
Rise Time
100% of I
PLLA
/I
PLLAA
10% - 90% of V
PLLA
/V
PLLAA
200
s
I
SD
Shut Down Current
1
A
I
CC
Short-circuit Current Threshold
170
mA
Table 1. Electrical Specifications (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
5
RE025 2.8V or 2.9V 30 mA LDO Voltage Regulator
2700BPMGMT02/03
Control Modes
All digital signals are referred to the supply voltage V
BAT3A/BAT3AA
.
Application
Example
A ceramic capacitor of 2.2 F with ESR between 20 m
and 250 m
connected from
V
PLLA
/V
PLLAA
to ground is needed for external compensation.
Figure 3. Application Example
Table 2. Truth Table
ON3
TRIMLDO3
V
PLLA
/V
PLLAA
0
X
Power down (High-Z)
1
0
Power on, V
PLLA
/V
PLLAA
= 2.8V
1
1
Power on, V
PLLA
/V
PLLAA
= 2.9V
Description
Min
Typ
Max
Units
Capacitor (C
L
)
1.8
2.2
2.6
F
Digital
Core
1.231V Bandgap
(e.g., BG019)
2.5V
2.5V Regulator
(e.g., RE031)
V
BAT3A
V
BAT3AA
V
PLLA
V
PLLAA
V
PLLS
V
SAUVC
V
BG
ON3
TRIMLDO3
V
PLLC
Battery
Pack
GND3
C
L
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