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Электронный компонент: T0353

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1
Features
AMPS/Cell Band and PCS Band CDMA/GPS Operation
Low-current Consumption
Excellent Noise and IP3 Performance
Adjustable Third Order intercept on LNA Stage
Flexible IF Frequency Range from 80 MHz to 230 MHz
Divide by 2 Prescaler
Benefits
Very Small 32-pin 5 mm x 5 mm Package
Few External Components
Fully ESD Protected
Applications
Quad-mode/Tri-band CDMA IS-95/98-based Mobile Phones with GPS Support
Electrostatic sensitive device.
Observe precautions for handling.
Description
The T0353 is a CDMA front-end receiver RFIC designed for Tri-band, quad-mode
operation. The device supports AMPS, Cell CDMA, PCS CDMA, and A-GPS opera-
tion. The IF range is from 80 MHz to 230 MHz with external tuning. The low-noise
amplifiers have an adjustable third order intercept point (IP3) to minimize inter-modu-
lation and cross-modulation effects. The mixers are designed for differential IF outputs
(single-ended or differential IF outputs for AMPS and GPS modes), and they feature
excellent linearity and low-noise figure.
The T0353 also integrates a divide-by-2 frequency divider to allow the use of only one
VCO module for both CDMA bands. However, it also has the option of connecting the
LO directly to the cellular mixer LO input. This device is available in a 5 mm x 5 mm
MLF package with 32 pins. The T0353 front-end receiver is capable of meeting all
electrical requirements in accordance with the TIA/EIA 98-C wireless communication
standard.
2.8 V Tri-band/
Quad-mode RF
Receiver for
CDMA/AMPS/
GPS
T0353
Preliminary
(Summary)
Rev. 4559ASCDMA10/02
2
T0353
4559ASCDMA10/02
Figure 1. Block Diagram
P_CLO_IN
CDMA_Out+
GLO_IN
BUFFEN
Gain
Band_SEL
L_IN
C
ontrol
PLNA_IN
CLNA_IN
AMPS IF+
Cell LO Out
PCS LO Out
PM
_In
CL
NA
OUT
CM

IN
GPS_M
i
x
IN
Vcc LNA
PLNA_GND
CL
NA
GND
Ise
t
_C
ell
3
7
6
5
26
2
1
31
9
27
25
4
29
30
24
23
21
20
12
14
11
15
AMPS IF-
Iset_PCS
32
/2
13
GPS_LNA_IN
GPS_LN
A OUT
M
i
x Vcc
8
10
16
22
19
18
GPS_MIX_Out+
GPS_MIX_Out-
CDMA_Out-
Vcc_Dig
PLNA O
U
T
Vcc LO TX
17
LO/2
28
3
T0353
4559ASCDMA10/02
Pin Configuration
Figure 2. Pinning
PLNA_GND
PLNA_IN
VCC_LNA
Gain
CLNA_OUT
CLNA_GND
CLNA_IN
GPS_LNA_IN
CDMA_OUT+
CDMA_OUT-
VCC_MIX
AMPS_OUT+
AMPS_OUT-
GPSMix_OUT+
GPSMix_OUT-
VCC_LO_TX
Isse
t_
PC
S
P
L
NA_OUT
LI
N
B
and_
S
E
L
V
CC_
DI
G
PM_
I
N
CM
_IN
BU
FF
EN
I
s
et
_Cel
l
G
PS_
L
N
A_
O
U
T
P_
C
L
O
_
IN
GLO_I
N
LO/
2
P
L
O_OUT
CL
O_OUT
GP
S
M
ix
_I
N
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Pin Description
Pin
Symbol
Function
1
PLNA_GND
PCS LNA emitter-ground. The LNA emitter ground should be grounded immediately to the ground-
plane to reduce stray inductance and capacitance that may affect performance.
2
PLNA_IN
PCS LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network
for optimum gain, intercept and noise performance.
3
Vcc_LNA
Power supply pin for PCS and Cell LNAs. Bypass with a capacitor as close to the pin as possible.
4
Gain
Gain select logic input for cellular band. Logic high selects High Gain.
5
CLNA_OUT
Cell LNA output. Requires a pull-up inductor to V
CC
and a series DC blocking capacitor, which can
be used as part of the output matching network.
6
CLNA_GND
Cell LNA emitter-ground. The LNA emitter ground should be grounded immediately to the ground-
plane to reduce stray inductance and capacitance that may affect performance.
7
CLNA_IN
Cell LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network
for optimum gain, intercept and noise performance.
8
GPS_LNA_IN
GPS LNA input. Requires a DC blocking capacitor and an L-C (shunt C/series L) matching network
for optimum gain, intercept and noise performance.
9
Iset_CELL
Bias resistor for Cell LNA. For typical bias use a 390
W
resistor to ground which sets the bias
current for HGHL mode.
10
GPS_LNA_OUT
GPS LNA output
.
11
P_CLO_IN
PCS and Cell band LO input.
12
GLO_IN
GPS LO input.
13
LO / 2
LO divider-select input. Low disables divider. High selects divider in cellular and AMPS modes.
14
PLO_OUT
PCS LO buffer output. Internally matched to 100
W
. Does not require a blocking capacitor.
4
T0353
4559ASCDMA10/02
Operation
The various operating modes are controlled by the logic inputs Band_SEL, Gain, LIN,
LO/2 and BUFFEN. Table 1 shows the pin settings for the various operating modes.
Table 1. Mode Programming Truth Table (Continued)
Note:
1. The symbol X ("do not care") means a logic input does not affect an operating mode.
15
CLO_OUT
Cellular LO buffer output. Internally matched to 100
W
. Does not require a blocking capacitor.
16
GPSMix_IN
GPS mixer input.
17
Vcc_LO_Tx
Supply voltage for LO buffers.
18
GPSMix_OUT-
Negative GPS IF output.
19
GPSMix_OUT+
Positive GPS IF output.
20
AMPS_OUT-
Negative AMPS IF output.
21
AMPS_OUT+
Positive AMPS IF output.
22
Vcc_Mix
Supply voltage for all mixers.
23
CDMA_OUT-
Negative CDMA IF output.
24
CDMA_OUT+
Positive CDMA IF output.
25
BUFFEN
LO output buffer enable. Set BUFFEN pin HIGH to power up the LO buffer output corresponding to
the selected band.
26
CM_IN
Cell RF input to Cell CDMA mixer and Cell AMPS mixer.
27
PM_IN
PCS mixer RF input.
28
Vcc_DIG
Supply voltage for logic control circuits.
29
Band_SEL
Logic input for band select. Logic LOW selects PCS or GPS. Logic HIGH selects cellular (AMPS).
30
LIN
Logic input for high or low linearity. Logic HIGH selects High linearity.
31
PLNA_OUT
PCS LNA output. Requires a pull-up inductor to V
CC
and a series blocking capacitor, which can be
used as part of the output matching network.
32
Iset_PCS
Bias resistor for PCS LNA. For typical bias use a 560
W
resistor to ground which sets the bias
current for HGHL mode.
Paddle
Device ground and heat sink, requires good thermal path; RF reference plane.
Pin Description (Continued)
Pin
Symbol
Function
Mode
Condition
Logic Inputs
(1)
Band SEL
Gain
LIN
LO/2
BUFFEN
Shut down
All circuits off
Low
Low
Low
X
X
PCS mode
High-gain, high-linearity
Low
High
High
X
X
High-gain, low-linearity
Low
High
Low
X
X
Activate PCS LO output buffer
Low
X
X
X
High
Cellular mode
High-gain, high-linearity
High
High
High
X
X
High-gain, low-linearity
High
High
Low
X
X
Low-gain
High
Low
High
X
X
AMPS mode
High
Low
Low
X
X
LO/2 On
High
X
X
High
X
Activate Cell LO output buffer
High
X
X
X
High
GPS mode
Low
Low
High
X
X
5
T0353
4559ASCDMA10/02
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Supply voltages, no RF applied
V
CC
-0.5 to +4.0
V
Logic control voltages
V
CTRL
-0.5 to +4.0
V
Supply current
I
CC
50.0
mA
RF and LO input signals
P
LO ;
C
LO;
CLNA_IN;
PLNA_IN; GPSLNA_IN;
+5.0 dBm
Storage temperature
T
STG
-55 to +150
C
Operating case temperature
T
C
-40 to +100
C
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
R
thJA
TBD
K/W
DC Supply Characteristics
Test conditions: Unless otherwise noted, the following conditions apply to typical performance specification under static
conditions (no RF applied): Vcc = +2.75 V, T
A
= 25C.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
All Modes
Supply voltage
2.7
2.75
3.3
V
Control voltage High
1.7
V
Control voltage Low
0.5
V
LO divider supply
current
I_CC LO/2 = High -
I_CC LO/2 = Low
1.7
mA
Cell LO Tx buffer
current
BUFFEN = High
6.0
mA
PCS LO Tx buffer
current
BUFFEN = High
8.5
mA
Logic-High current
100
A
Logic-Low current
-5.0
A
Power-down supply
current
Band_SEL, Gain, LIN
= Low
10
A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter