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Электронный компонент: T48C510

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T48C510
Preliminary Information
Rev. A2, 26-Feb-01
1 (61)
MARC4 4-bit MTP Universal Microcontroller
The T48C510 is an Multi Time Programmable (MTP) microcontroller which is pin and functionally compatible to the
Atmel Wireless & Microcontrollers' M44C510E mask programmable microcontroller. It contains EEPROM, RAM,
up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer,
interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock
module.
Features / Benefits
D Programmable system clock with prescaler and five
different clock sources:
Up to 8-MHz crystal oscillator (system clock)
32-kHz crystal oscillator
RC-oscillator fully integrated
RC-oscillator with external resistor adjustment
External clock input
D Wide supply-voltage range (2.4 V to 6.2 V)
D Very low halt current
D 4 KByte program EEPROM, 256 x 4-bit RAM
D 8 hard- and software interrupt priority levels
D Up to 10 external and 4 internal interrupts, bitwise
maskable with programmable priority level
D Up to 34 I/O lines
D I/O ports bitwise configurable with combined inter-
rupt handling (for serial I/O applications)
D 2 x 8-bit multifunction timer/counters
D Coded reset and watchdog timer
D Power-on reset and "brown out" function
D Various power-down modes
D Efficient, hardware-controlled interrupt handling
D High-level programming language in qFORTH
D Comprehensive library of useful routines
D Windows 95/NT based development and programmer
tools
MARC4
System
clock
Timer/
counter
Timer 0
Timer 1
Master
reset
TE
Port 0 Port 1 Port 5
Port B
SCLIN
I/O bus
EEPROM
RAM
4-bit CPU core
4K x 8 bit
256 x 4 bit
Watch
dog
I/O
I/O
I/O
Test
Sleep
NRST
VDD
Port 7
Port A
I/O
Port 4
I/O
Interrupt
& reset
Prescaler
AVDD
I/O
I/O
Interrupt
I/O
Interrupt
Port 6
Real time
clock
OSCIN OSCOUT
Melody
& buzzer
TIM1
16536
I/O
Port C
4
4
4
4
4
4
4
4
2
VSS
Config.
EEPROM
PM
Figure 1. Block diagram
T48C510
Rev. A2, 26-Feb-01
Preliminary Information
2 (61)
Ordering Information
Extended Type Number
Package
Remarks
T48C510 ILS
SSO44
Stick
T48C510 ILQ
SSO44
Taped and reeled
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SC
L
I
N
BP
C
0
BP
0
0
BP
1
2
BP
1
1
BP
1
0
OSCIN
OSCOUT
BP
0
1
BP
0
2
BP
0
3
NR
S
T
V
SS
VDD
BP
4
3
BP
4
2
BP
4
1
BP
4
0
BP
B3
BP
B2
BP
B1
BP
B0
BP
7
0
BP
7
1
BP
7
2
BP
7
3
BP
5
3
BP
5
2
BP
5
1
BP
5
0
TI
M1
BP
A
3
BP
A
2
BP
A
1
BP
A
0
TE
AVDD
BP
6
1
BP
6
0
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
23
24
41
42
43
44
BPC1
BP
1
3
PM
BPC3
BPC2
T48C510
Figure 2. Pin connections SSO44-package
Table 1 Pin description
Name
Function
V
DD
Power supply voltage +2.4 V to +6.2 V
AV
DD
Analog power supply voltage +2.4 V to +6.2 V
V
SS
Circuit ground
BP00 BP03
4 I/O lines of Port 0 automatic nibblewise configurable / programmer interface
BP10 BP13
4 I/O lines of Port 1 automatic nibblewise configurable
BP50 BP53
4 I/O lines of high current Port 5 bitwise configurable
BP70 BP73
4 I/O lines of high current Port 7 bitwise configurable
BPA0 BPA3
4 I/O lines of Port A bitwise configurable, as inputs to a port monitor module and optional
coded reset inputs
BPB0 BPB3
4 I/O lines of Port B bitwise configurable I/O and as inputs to a port monitor module
BPC0 BPC3
4 I/O lines of Port C bitwise configurable I/O
BP60 BP61
2 I/O lines of Port 6 bitwise configurable I/O or as external programmable interrupts
BP40 (T0OUT0)
I/O line BP40 of Port 4 configurable or timer/counter I/O T0OUT0
BP41 (T0OUT1)
I/O line BP41 of Port 4 configurable or timer/counter I/O T0OUT1
BP42 (BUZ)
High current I/O line BP42 of Port 4 configurable or buzzer output BUZ
BP43 (NBUZ)
High current I/O line BP43 of Port 4 configurable or buzzer output NBUZ
TIM1
Dedicated I/O for Timer 1
SCLIN
External trimming resistor or external clock input
OSCIN
32-kHz quartz crystal or 4-MHz quartz crystal input pin
OSCOUT
32-kHz quartz crystal or 4-MHz quartz crystal output pin
TE
Testmode input, used to control the production test modes (internal pull-down)
NRST
Reset input (/output), a logic low on this pin resets the device. An internal watchdog or
coded reset can cause a low pulse on this pin.
PM
MTP program mode enable pin (internal pull-down)
T48C510
Preliminary Information
Rev. A2, 26-Feb-01
3 (61)
Table of Contents
1
MARC4 Architecture
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
General Description
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Components of MARC4 Core
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
EEPROM
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
RAM
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3
Registers
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
ALU
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.5
Instruction Set
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.6
I/O Bus
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Interrupt Structure
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Hardware Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Software Interrupts
11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Hardware Reset
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Clock Generation
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
Clock Module
13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2
Oscillator Circuits and External Clock Input Stage
14
. . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock
14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor
14
. . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Oscillator Configuration
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3
Clock Management Register (CM)
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC)
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4
Power-down Modes
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5
Clock Monitor Mode
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Peripheral Modules
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Addressing Peripherals
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Bidirectional Ports
21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Bidirectional Port 0 and Port 1
22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Bidirectional Port 5, Port 7 and Port C
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Bidirectional Port A and Port B with Port Monitor Function
23
. . . . . . . . . . . . . . . .
2.2.4
Bidirectional Port 6
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Bidirectional Port 4
27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
TIM1 Dedicated Timer 1 I/O Pin
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Interval Timers / Prescaler
28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Interval Timer Registers
29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Watchdog Timer
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Timer/Counter Module (TCM)
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
General Timer/Counter Control Registers
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Timer/Counter in 16-bit Mode
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Timer 0 Modes
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Timer 1 Modes
44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T48C510
Rev. A2, 26-Feb-01
Preliminary Information
4 (61)
Table of Contents (continued)
2.6
Buzzer Module
47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
MTP Programming
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8
Noise Considerations
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
Noise Immunity
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2
Electromagnetic Emission
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Electrical Characteristics
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
DC Operating Characteristics
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
AC Characteristics
53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Device Information
57
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Pad Layout
57
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Packaging
58
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Hardware Options
59
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T48C510
Preliminary Information
Rev. A2, 26-Feb-01
5 (61)
1
MARC4 Architecture
Instruction
decoder
CCR
TOS
ALU
RAM
PC
RP
SP
X
Y
Program
256 x 4-bit
MARC4 CORE
Clock
Reset
Sleep
Memory bus
I/O bus
Instruction
bus
Reset
System
clock
Interrupt
controller
Onchip peripheral modules
94 8973
memory
Figure 3. MARC4 core
1.1
General Description
The functionality, programming and pinning of the
T48C510 is compatible with the M44C510E mask pro-
grammable microcontroller from Atmel Wireless &
Microcontrollers. All on-chip modules are addressed and
controlled with exactly the same programming code, so
that a program targeted for the M44C510E can be read
directly into the T48C510 and will operate in the same
fashion.
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physi-
cally separate program memory (EEPROM) and data
memory (RAM). Three independent buses, the instruc-
tion bus, the memory bus and the I/O bus are used for
parallel communication between EEPROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language pro-
gramming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains EEPROM, RAM, ALU, a program
counter, RAM address registers, an instruction decoder
and an interrupt controller. The following sections de-
scribe each functional block in more detail:
1.2.1
EEPROM
The program memory (EEPROM) is programmed with
the customer application program. The EEPROM is ad-
dressed by a 12-bit wide program counter, thus
predefining a maximum program bank size of 4 Kbytes.