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Features
Contactless Read/Write Data Transmission
Radio Frequency f
RF
from 100 kHz to 150 kHz
e5550 Binary Compatible or T5557 Extended Mode
Small Size, Configurable for ISO/IEC 11784/785 Compatibility
75 pF On-chip Resonant Capacitor (Mask Option)
7 x 32-bit EEPROM Data Memory Including 32-bit Password
Separate 64-bit memory for Traceability Data
32-bit Configuration Register in EEPROM to Setup:
Data Rate
- RF/2 to RF/128, Binary Selectable or
- Fixed e5550 Data Rates
Modulation/Coding
- FSK, PSK, Manchester, Biphase, NRZ
Other Options
- Password Mode
- Max Block Feature
- Answer-On-Request (AOR) Mode
- Inverse Data Output
- Direct Access Mode
- Sequence Terminator(s)
- Write Protection (Through Lock-bit per Block)
- Fast Write Method (5 kbps versus 2 kbps)
- OTP Functionality
- POR Delay up to 67 ms
Description
The T5557 is a contactless R/W IDentification IC (IDIC
) for applications in the
125 kHz frequency range. A single coil, connected to the chip, serves as the IC's
power supply and bi-directional communication interface. The antenna and chip
together form a transponder or tag.
The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written block-
wise from a reader. Block 0 is reserved for setting the operation modes of the T5557
tag. Block 7 may contain a password to prevent unauthorized writing.
Data is transmitted from the IDIC
using load modulation. This is achieved by damping
the RF field with a resistive load between the two terminals Coil 1 and Coil 2. The IC
receives and decodes 100% amplitude modulated (OOK) pulse interval encoded bit
streams from the base station or reader.
System Block Diagram
Figure 1. RFID System Using T5557 Tag
Base station
Data
Power
Transponder
Reader
or
Base station
Data
T5557
Power
*
Mask option
*
Con
t
r
o
l
l
er
C
o
il
i
n
te
r
f
a
c
e
Memory
Multifunctional
330-bit
Read/Write
RF-Identification
IC
T5557
Rev. 4517ERFID02/03
2
T5557
4517ERFID02/03
T5557
Building Blocks
Figure 2. Block Diagram
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the
IC's power supply and handles the bi-directional data communication with the reader. It
consists of the following blocks:
Rectifier to generate a DC supply voltage from the AC coil voltage
Clock extractor
Switchable load between Coil 1/Coil 2 for data transmission from tag to the reader
Field gap detector for data transmission from the base station to the tag
ESD protection circuitry
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and
RF/128 or equal to any of the fixed e5550/e5551 and T5554 bitrates (RF/8, RF/16,
RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128).
Write Decoder
This function decodes the write gaps and verifies the validity of the data stream
according to the Atmel e555x write method (pulse interval encoding).
HV Generator
This on-chip charge pump circuit generates the high voltage required for programming
of the EEPROM.
DC Supply
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and
regulates this RF source and uses it to generate its supply voltage.
*
Mask option
*
Coil 1
Coil 2
Modulator
A
n
a
l
o
g

f
r
o
n
t

e
n
d
POR
Input register
W
r
i
t
e
d
e
c
o
d
e
r
B
i
t
-
r
a
t
e
g
e
n
e
r
a
t
o
r
Memory
(330 bit EEPROM)
Controller
Test logic
Mode register
HV generator
3
T5557
4517ERFID02/03
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been
reached.
Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
Controller
The control-logic module executes the following functions:
Load-mode register with configuration data from EEPROM block 0 after power-on
and also during reading
Control memory access (read, write)
Handle write data transmission and write error modes
The first two bits of the reader to tag data stream are the opcode, e.g., write, direct
access or reset
In password mode, the 32 bits received after the opcode are compared with the
password stored in memory block 7
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is
continually refreshed at the start of every block read and (re-)loaded after any POR
event or reset command. On delivery the mode register is preprogrammed with the
value `0014 8000'h which corresponds to continuous read of block 0, Manchester
coded, RF/64.
Figure 3. Block 0 Configuration Mapping e5550 Compatibility Mode
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
RF/8
RF/16
RF/32
RF/40
RF/50
RF/64
RF/100
RF/128
ST-Sequence Ter
m
inator
Safer Key
Note 1), 2)
L 1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 1 1 0 0 0 0 0 0 0 0
0
0
0 0
Data
Bit Rate
0 0
0 1
1 0
1 1
RF/2
RF/4
RF/8
Res.
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
1 0 0 0 0
1 1 0 0 0
Direct
PSK1
PSK2
PSK3
FSK1
FSK2
FSK1a
FSK2a
Manchester
Biphase('50)
Reserved
PSK-
CF
AOR
MAX-
BLOCK
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key <> 6 or 9 then extended function mode is disabled
Modulation
0 Unlocked
1 Locked
Loc
k Bit
PWD
POR
delay
4
T5557
4517ERFID02/03
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 1. Types of e5550-compatible Modulation Modes
Notes: 1. A common multiple of bitrate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK
sub-carrier frequency.
Memory
The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33
bits of a block, including the lock bit, are programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during
regular-read operations. Block 7 of page 0 may be used as a write protection password.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the
lock bit itself) is not re-programmable through the RF field again.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modula-
tion parameters defined in the configuration register after the opcode '11' is issued by
the reader (see Figure 11). These tracebility data blocks are programmed and locked by
Atmel.
Figure 4. Memory Map
Mode
Direct Data Output
FSK1a
(1)
FSK/8-/5
`0' = rf/8;
`1' = rf/5
FSK2a
(1)
FSK/8-/10
`0' = rf/8;
`1' = rf/10
FSK1
(1)
FSK/5-/8
`0' = rf/5;
`1' = rf/8
FSK2
(1)
FSK/10-/8
`0' = rf/10;
1' = rf/8
PSK1
(2)
Phase change when input changes
PSK2
(2)
Phase change on bit clock if input high
PSK3
(2)
Phase change on rising edge of input
Manchester
`0' = falling edge, `1' = rising edge
Biphase
`1' creates an additional mid-bit change
NRZ
`1' = damping on, `0' = damping off
L
L
L
L
L
L
L
L
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
User data or password
32 bits
User data
User data
User data
User data
User data
User data
Configuration data
1
32
0
Not transmitted
Block 2
Block 1
Traceability data
Traceability data
1
1
P
age
1
Pag
e
0
5
T5557
4517ERFID02/03
Traceability Data
Structure
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked
by Atmel during production testing. The most significant byte of block 1 is fixed to
`E0'hex, the allocation class (ACL) as defined in ISO/IEC 15963-1. The second byte is
therefore defined as the manufacturer's ID of Atmel (= `15'hex). The following 8 bits are
used as IC reference byte (ICR - Bits 47 to 40). The 3 most significant bits define the IC
and/or foundry version of the T5557. The lower 5 bits are by default reset (=00) as the
Atmel standard value. Other values may be assigned on request to high volume custom-
ers as tag issuer identification.
The lower 40 bits of the data encode the traceability information of Atmel and conform to
a unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit
lot ID number, the binary wafer number (5 bit) concatenated with the sequential die
number per wafer.
Figure 5. T5557 Traceability Data Structure
ACL
Allocation class as defined in ISO/IEC 15963-1 = E0h
MFC
Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h
ICR
IC reference of silicon and/or tag manufacturer
Top 3 bits define IC revision
Lower 5 bits may contain a customer ID code on request
MSN
Manufacturer serial number consists of:
LotID
5-digit lot number, e.g., '38765'
DPW
20 bits encoded as sequential die per wafer number (with top 5 bits = wafer#)
Operating the T5557
Initialization and
POR Delay
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold
has been reached. This in turn triggers the default start-up delay sequence. During this
configuration period of about 192 field clocks, the T5557 is initialized with the configura-
tion data stored in EEPROM block 0. During initialization of the configuration block 0, all
T55570x variants the load damping is active permanently (see Figure 10). The T55571x
types (without damping option) achieve a longer read range based on the lower activa-
tion field strength.
If the POR-delay bit is reset, no additional delay is observed after the configuration
period. Tag modulation in regular-read mode will be observed about 3 ms after entering
the RF field. If the POR delay bit is set, the T5557 remains in a permanent damping
state until 8190 internal field clocks have elapsed.
T
INIT
= (192 + 8190
POR delay)
T
C
67 ms ; T
C
= 8 s at 125 kHz
12
32
31
1
...
13 ...
Traceability
wafer #
MFC
ICR
Block 2
Block 1
1
...
8
16 17
9
...
ACL
MSN LotID
...
24
20
12
25
...
32
8
die on wafer #
LotID
18 19
...
Example:
' E0 '
' 15 '
' 00 '
' 41 '
' 557 '