Features

Frequency Receiving Range of
f

= 868 MHz to 870 MHz or f

= 902 MHz to 928 MHz

30 dB Image Rejection

Receiving Bandwidth B

= 600 kHz for Low Cost 90-ppm Crystals

Fully Integrated LC-VCO and PLL Loop Filter

Very High Sensitivity with Power Matched LNA

High System IIP3 (-16 dBm), System 1-dB Compression Point (-25 dBm)

High Large-signal Capability at GSM Band
(Blocking -30 dBm at +20 MHz, IIP3 = -12 dBm at +20 MHz)

5 V to 20 V Automotive Compatible Data Interface

Data Clock Available for Manchester- and Bi-phase-coded Signals

Programmable Digital Noise Suppression

Low Power Consumption Due to Configurable Polling

Temperature Range -40

C to +105

ESD Protection 2 kV HBM, All Pins

Communication to Microcontroller Possible Via a Single Bi-directional Data Line

Low-cost Solution Due to High Integration Level with Minimum External Circuitry
Requirements

Description

The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It
has been especially developed for the demands of RF low-cost data transmission
systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code.
The receiver is well suited to operate with the Atmel's PLL RF transmitter T5750. Its
main applications are in the areas of telemetering, security technology and keyless-
entry systems. It can be used in the frequency receiving range of f

= 868 MHz to

870 MHz or f

= 902 MHz to 928 MHz for ASK or FSK data transmission. All the state-

ments made below refer to 868.3 MHz and 915.0 MHz applications.

Figure 1. System Block Diagram

Demod.

IF Amp

LNA

VCO

PLL

XTO

Control

T5760/

T5761

1...5

µC

Power

amp.

XTO

VCO

PLL

T5750

Antenna

UHF ASK/FSK

Remote control transmitter

UHF ASK/FSK

Remote control receiver

UHF ASK/FSK
Receiver

T5760/T5761

Preliminary

Rev. 4561BRKE10/02

T5760/T5761

4561BRKE10/02

Pin Configuration

Figure 3. Pinning SO20

AVCC

TEST 1

AGND

n.c.

LNAREF

LNA_IN

IC_ACTIVE

CDEM

DATA_CLK

TEST 4

XTAL

n.c.

TEST 3

POLLING/_ON

DGND

LNAGND

TEST 2

DATA

DVCC

SENS

T5760/

T5761

Pin Description

Pin

Symbol

Function

SENS

Sensitivity-control resistor

IC_ACTIVE

IC condition indicator: Low = sleep mode, High = active mode

CDEM

Lower cut-off frequency data filter

AVCC

Analog power supply

TEST 1

Test pin, during operation at GND

AGND

Analog ground

n.c.

Not connected, connect to GND

LNAREF

High-frequency reference node LNA and mixer

LNA_IN

RF input

LNAGND

DC ground LNA and mixer

TEST 2

Do not connect during operating

TEST 3

Test pin, during operation at GND

n.c.

Not connected, connect to GND

XTAL

Crystal oscillator XTAL connection

DVCC

Digital power supply

TEST 4

Test pin, during operation at DVCC

DATA_CLK

Bit clock of data stream

DGND

Digital ground

POLLING/_ON

Selects polling or receiving mode; Low: receiving mode, High: polling mode

DATA

Data output/configuration input

T5760/T5761

4561BRKE10/02

RF Front End

The RF front end of the receiver is a low-IF heterodyne configuration that converts the
input signal into a 950 kHz/1 MHz IF signal with an image rejection of typical 30 dB.
According to Figure 3 the front end consists of an LNA (Low Noise Amplifier), LO (Local
Oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier.

The PLL generates the carrier frequency for the mixer via a full integrated synthesizer
with integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter.
The XTO (crystal oscillator) generates the reference frequency f

XTO

. The integrated LC-

VCO generates two times the mixer drive frequency f

VCO

. The I/Q signals for the mixer

are generated with a divide by two circuit (f

= f

VCO

/2). f

VCO

is divided by a factor of 256

and feeds into a phase frequency detector and compared with f

XTO

. The output of the

phase frequency detector is fed into an integrated loop filter and thereby generates the
control voltage for the VCO. If f

is determined, f

XTO

can be calculated using the follow-

ing formula:

XTO

= f

/128

The XTO is a one-pin oscillator that operates at the series resonance of the quartz
crystal with high current but low voltage signal, so that there is only a small voltage at
the crystal oscillator frequency at Pin XTAL. According to Figure 4, the crystal should be
connected to GND with a series capacitor C

. The value of that capacitor is recom-

mended by the crystal supplier. Due to a somewhat inductive impedance at steady state
oscillation and some PCB parasitics a lower value of C

is normally necessary.

The value of C

should be optimized for the individual board layout to achieve the exact

value of f

XTO

(the best way is to use a crystal with known load resonance frequency to

find the right value for this capacitor) and hereby of f

. When designing the system in

terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal
and the XTO must be considered.

If a crystal with ±30 ppm adjustment tolerance at 25

C, ±50 ppm over temperature

-40

C to +105

C, ±10 ppm of total aging and a CM (motional capacitance) of 7 fF is

used, an additional XTO pulling of ±30 ppm has to be added.

The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth
specification of the T5760/T5761 if the T5750 has also a total LO tolerance of
±120 ppm.

Figure 4. XTO Peripherals

The nominal frequency f

is determined by the RF input frequency f

and the IF

frequency f

using the following formula (low side injection):

= f

- f

DVCC

XTAL

TEST 3

TEST 2

n.c.

T5760/T5761

4561BRKE10/02

To determine f

, the construction of the IF filter must be considered at this point. The

nominal IF frequency is f

= 950 kHz. To achieve a good accuracy of the filter corner

frequencies, the filter is tuned by the crystal frequency f

XTO

. This means that there is a

fixed relation between f

and f

= f

/915

The relation is designed to achieve the nominal IF frequency of f

= 950 kHz for the

868.3 MHz version. For the 915 MHz version an IF frequency of f

= 1.0 MHz results.

The RF input either from an antenna or from an RF generator must be transformed to
the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical
parameters. The parasitic board inductances and capacitances influence the input
matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is
power matched. This makes the matching to an SAW filter as well as to 50

or an

antenna easier.

Figure 33 shows a typical input matching network for f

= 868.3 MHz to 50

. Figure 34

illustrates an according input matching for 868.3 MHz to an SAW. The input matching
network shown in Figure 33 is the reference network for the parameters given in the
electrical characteristics.

Analog Signal Processing

IF Filter

The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF
filter. The IF center frequency is f

= 950 kHz for applications where f

= 868.3 MHz

and f

=1.0 MHz for f

= 915 MHz. The nominal bandwidth is 600 kHz.

Limiting RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is
fed into the demodulator. The dynamic range of this amplifier is DR

RSSI

= 60 dB. If the

RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier,
because only the hard limited signal from a high gain limiting amplifier is used by the
demodulator.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage
V

Th_red

. V

Th_red

is determined by the value of the external resistor R

Sens

. R

Sens

is con-

nected between Pin SENS and GND or V

. The output of the comparator is fed into the

digital control logic. By this means it is possible to operate the receiver at a lower
sensitivity.

If R

Sens

is connected to GND, the receiver switches to full sensitivity. It is also possible to

connect the Pin SENS directly to GND to get the maximum sensitivity.

If R

Sens

is connected to V

, the receiver operates at a lower sensitivity. The reduced

sensitivity is defined by the value of R

Sens

, the maximum sensitivity by the signal-to-

noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at
the output of the RSSI amplifier.

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