Rev. 4531BBCD11/03
Features
Supply Voltage up to 40 V
R
DSon
Typically 0.5
at 25
C, Maximum 1
at 150
C
Up to 1.5 A Output Current
Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges
Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
PWM Capability for Each Output Controlled by External PWM Signal
No Shoot-through Current
Very Low Quiescent Current I
S
< 5 A in Standby Mode over Total Temperature Range
Outputs Short-circuit Protected
Selective Overtemperature Protection for Each Switch and Overtemperature
Prewarning
Undervoltage Protection
Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
SO16 Power Package
Description
The T6819/T6829 are fully protected driver interfaces designed in 0.8-m BCDMOS
technology. They are used to control up to six different loads by a microcontroller in
automotive and industrial applications.
Each of the three high-side and three low-side drivers is capable to drive currents up
to 1.5 A. Each driver is freely configurable and can be controlled separately from a
standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors,
capacitors and inductors can be combined.
The IC design especially supports the
applications of H-bridges to drive DC motors. The capability to control each output
with an external PWM signal opens additional applications.
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in stand-by
mode opens a wide range of applications. Automotive qualification (protection against
conducted interferences, EMC protection and 2-kV ESD protection) gives added value
and enhanced quality for exacting requirements of automotive applications.
Dual Triple
DMOS Output
Driver with
Serial Input
Control
T6819/T6829
Preliminary
2
T6819/T6829 [Preliminary]
4531BBCD11/03
Figure 1. Block Diagram
OUT1H
OUT2H
OUT3H
DI
CLK
DO
CS
PWM
UV -
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
S
I
O
L
D
P
S
F
I
N
H
O
V
L
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
Fault
detect
GND
GND
VS
OUT1L
OUT2L
OUT3L
VCC
Thermal
protection
Control
logic
Power-on
reset
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
GND
pump
Charge
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
O
C
S
3
15
2
13
14
4
5
10
8
6
7
12
1
9
16
11
Fault
detect
Fault
detect
Fault
detect
Fault
detect
Fault
detect
3
T6819/T6829 [Preliminary]
4531BBCD11/03
Pin Configuration
Figure 2. Pinning SO16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OUT1L
OUT3L
OUT3H
CS
DI
CLK
PWM
GND
OUT2L
OUT2H
OUT1H
VS
VCC
DO
GND
Pin Description
Pin
Symbol
Function
1
GND
T6819: ground; reference potential; internal connection to pin 9 and pin 16; cooling tab
T6829: additional connection to heat slug
2
OUT1L
Low-side driver output 1; power MOS open drain with internal reverse diode; short-circuit protection;
overtemperature protection; diagnosis for short and open load; PWM ability
3
OUT3L
Low-side driver output 3; see pin 2
4
OUT3H
High-side driver output 3; power MOS open source with internal reverse diode; short-circuit protection;
overtemperature protection; diagnosis for short and open load; PWM ability
5
CS
Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
6
DI
Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
7
CLK
Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
8
PWM
PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs
which are selected for PWM mode by the serial data interface, high = outputs on, low = outputs off
9
GND
Ground; see pin 1
10
DO
Serial data output; 5-V CMOS logic-level tristate output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tristated unless
device is selected by CS = low, therefore, several ICs can operate on one data-output line only.
11
VCC
Logic supply voltage (5 V)
12
VS
Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply
13
OUT1H
High-side driver output 1; see pin 4
14
OUT2H
High-side driver output 2; see pin 4
15
OUT2L
Low-side driver output 2; see pin 2
16
GND
Ground; see pin 1
4
T6819/T6829 [Preliminary]
4531BBCD11/03
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, pin DO is in tristate condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data Transfer
Table 1. Input Data Protocol
SRR
LS1
HS1
LS2
HS2
LS3
HS3
PL1
PH1
PL2
PH2
PL3
PH3
OLD
OCS
SI
CS
DI
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVL
INH
PSF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit
Input Register
Function
0
SRR
Status register reset (high = reset; the bits PSF and OVL in the
output data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
PL1
Output LS1 additionally controlled by PWM Input
8
PH1
Output HS1 additionally controlled by PWM Input
9
PL2
See PL1
10
PH2
See PH1
11
PL3
See PL1
12
PH3
See PH1
13
OLD
Open load detection (low = on)
14
OCS
Overcurrent shutdown (high = overcurrent shutdown is active)
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the
digital part is still powered)
5
T6819/T6829 [Preliminary]
4531BBCD11/03
Table 2. Output Data Protocol
After power-on reset, the input register has the following status:
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit
Output (Status)
Register
Function
0
TP
Temperature prewarning: high = warning
1
Status LS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
2
Status HS1
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
3
Status LS2
Description see LS1
4
Status HS2
Description see HS1
5
Status LS3
Description see LS1
6
Status HS3
Description see HS1
7
n. u.
Not used
8
n. u.
Not used
9
n. u.
Not used
10
n. u.
Not used
11
n. u.
Not used
12
n. u.
Not used
13
OVL
Over-load detected: set high, when at least one output is switched
off by a short-circuit condition or an overtemperature event. Bits 1
to 6 can be used to detect the affected switch.
(open-load detection bit OLD = high)
14
INH
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
15
PSF
Power-supply fail: undervoltage at pin VS detected
Bit 15
SI
Bit 14
OCS
Bit 13
OLD
Bit 12
PH3
Bit 11
PL3
Bit 10
PH2
Bit 9
PL2
Bit 8
PH1
Bit 7
PL1
Bit 6
HS3
Bit 5
LS3
Bit 4
HS2
Bit 3
LS2
Bit 2
HS1
Bit 1
LS1
Bit 0
SRR
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Bit 15
Bit 14
Bit 13
(OCS)
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
L
L
L
L
L
L
L
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