Rev. C24-Aug-01
1
Features
Initialization of the Program Memory by DMA via the User Extension Interface (8-bit or
16-bit data format possible) or via the Synchronous Serial Input Link 1 (16-bit data
format),
SRAM and DRAM support
Write access protection
40-bit User Extension interface
Automatic conversion to and from a 32-bit data User Extension Interface
Powerful 16-bit programmable versatile IO port featuring 2 input/output serial ports, up
to 16-bit input/output parallel port, 4 pulse generators, 2 full duplex UART
Four External interrupts
Two 32-bit timers
Watch Dog
Two CRC accelerators (one for the input data stream, one for the output data stream)
JTAG
Maximum Operating frequency: 40MHz for ClkIn
Power Consumption: 350 mA at 40MHz for ClkIn
Latch Up immunity better than 100 MeV
Designed on Atmel M62265E matrix sea of gates, into an MQFPF256
Introduction
After Atmel successfully released the TSC21020F DSP, a code and pin compatible
radiation hard version (including SEU hardening) of the ADI ADSP-21020, ASTRIUM
have, under an ESA contract, developed a TSC21020F companion chip called DSP
Peripheral Controller (DPC).
This DSP Peripheral Controller is a generic support device suitable for on-board appli-
cations using the TSC21020F processor. The device implements those support
functions which are required for the integration of the processor with other devices in a
board design.
It has been designed on the Atmel MG2RT Sea of Gates series, allowing to have a
DPC chip hardened almost at the same level as the TSC21020F is, latch up and total
dose wise.
The T7904E is now available from Atmel as a standard ASIC. It is available in a 256-
pin MQFPF ceramic package.
Radiation
Tolerant DSP
Peripheral
Controller
T7904E
2
T7904E
Rev. C24-Aug-01
Figure 1. Functional block diagram of the T7904E
Data Memory
Sequencer
Data Memory
Address Decoder
and Controls
Data Memory
Data Parity
Generation
Program Memory
Address Decoder
and Controls
Program Memory
Sequencer
Program Memory
Data Parity
Generation
Flexible IO port including:
- serial links coupled to FIFO and / or CRC
- parallel ports
- UARTs
- pulse genrators
User Extension
Interface Control
WatchDog
Interrupt
Controller
2 32-bit Timers
Clock + Reset
JTAG
User Extension
Interface Control
Signal
Parity bit for
Data Memory
Parity and Check
bits for Program
Memory
External Interrupt
Interface
16-bit flexible
IO port
DRAM Control
Signal
Control Signal
for Programs
Memory
DPC internal
registers
Interrupt
Request to DSP
DSP Data
Memory
Interface
DSP Program
Memory
Interface
Internal Data Bus
Internal Data Bus
Register Selection
+ control signal
Clock, Reset
JTAG
Interface
4 * FIFO 256 x 32
3
T7904E
Rev. C24-Aug-01
Typical DSP core architecture based on the T7904E
This section presents 2 typical DSP core architectures implementing the T7904E.
DSP Processor Core
Architecture: SRAM
implementation
This architecture is based on a parallel data bus approach. The DSP Processor core
implements the following discrete circuits on a PCB:
the TSC21020 DSP,
the T7904E,
SRAMs for both the Program Memory and the Data Memory (optional parity
protection),
transceivers on the address and data bus of the User Extension Interface
(the control signal of this interface are directly generated by the T7904E).
Figure 2. DSP Processor Core Architecture: SRAM implementation
DSP Processor Core
Architecture: DRAM
implementation
This architecture is quite similar to the previous one, except that the Data Memory
(DMBANK0) is made up of DRAMs.
Program Memory
(SRAM implementation)
Data Memory
(SRAM implementation)
21020 DSP
Program
Memory
Interface
Data
Memory
Interface
Parity bit
Address bus
Control bus
48-bit data bus
Buffer
Address bus
Control bus
40-bit data bus
40-bit data bus
Address bus
Parity bit
T7904E
Flexible
IO Port
User
Extension
Interface
Chip Select
+ Ctrl
Data
Address
External
Interrupts
16 bits
Interrupt Request
JTAG Interface
Parity bit
Parity bit
FIFO
Interface
16 bits
4
T7904E
Rev. C24-Aug-01
Figure 3. DSP Processor Core Architecture: DRAM implementation
Program Memory
(SRAM implementation)
Data Memory
(DRAM implementation)
21020 DSP
Program
Memory
Interface
Data
Memory
Interface
Parity bit
Address bus
Control bus
48-bit data bus
Buffer
Address bus
Control bus
40-bit data bus
40-bit data bus
Address bus
Parity bit
T7904E
Flexible
IO Port
User
Extension
Interface
Chip Select
+ Ctrl
Data
Address
External
Interrupts
16 bits
Interrupt Request
JTAG Interface
Parity bit
Parity bit
RAS*/CAS*
FIFO
Interface
20 bits
5
T7904E
Rev. C24-Aug-01
Functional description
Program Memory
initialization
The T7904E can initialize the program memory according to a predefined
configuration. The configuration is selected by reading the PMD(1-0) data bus in the
last cycle of the reset phase:
1.
PMD(1-0) = 00: No Program Memory Initialization is performed by the
T7904E,
2.
PMD(1-0) = 01: The Program Memory Initialization is done via the data bus
DMD(15-8) of IO Area 0 for the flat package T7904E: 8-bit width,
3.
PMD(1-0) = 10: The Program Memory Initialization is done via the data bus
DMD(23-8) of IO Area 0 for the flat package T7904E: 16-bit width,
4.
PMD(1-0) = 11: The Program Memory Initialization is done via the Synchro-
nous Serial Input Link 1: 16-bit width.
When the Program Memory Initialization is done via the IO Area 0 or via the
Synchronous Serial Input Link 1, the 20 lsb of the first 6 x 8 bytes that are fetched,
indicate the number of 48-bit words to be loaded in the Program Memory RAM. The
least significant byte of the 48-bit words are fetched first. Each time a new byte is
fetched, it is stored in the Program Register named PrgReg(47-0), the first byte in
PrgReg(7-0), the second byte in PrgReg(15-8), the third byte in PrgReg(23-16), the
fourth byte in PrgReg(31-24), the fifth byte in PrgReg(39-32) and the sixth byte in
PrgReg(47-40). When 6 bytes are available in PrgReg, the T7904E performs a DMA
access to write the content of PrgReg(47-0) into the Program Memory RAM.
During the Program Memory initialization, the T7904E generates the parity bit
PMPar over PMD(47-0) if required.
As soon as the Program Memory initialization is completed, the DSP can set the bit
SysAv in the General Configuration Register (GConfReg). The value of SysAv in
GConfReg is reflected on the output signal SysAv to indicate the system is
available.
Memory Organization
The Data Memory interface is organized into 4 identical banks DMBANK0,
DMBANK1, DMBANK2, DMBANK3 corresponding to the Data Memory banks
defined in the TSC21020 User's manual:
1.
DMBANK0 is dedicated to the Data Memory RAM. The T7904E supports to
implement DRAM devices or SRAM devices in the DMBANK0. DMBANK0 is
a 40-bit data bus area,
2.
DMBANK1 provides 4 identical areas which size is 4Mwords for User Exten-
sions. Each area is decoded by a specific selection signal IOSel*(3-0). The
T7904E implements its internal registers in DMBANK1. DMBANK1 is a 40-
bit data bus area except the T7904E internal register area which is a 32-bit
data bus area,
3.
DMBANK2 and DMBANK3 are 40-bit data bus areas.
The T7904E supports to perform a 32-bit data bus automatic conversion to and from
8-bit/16-bit data bus on the sub-areas IOArea0, IOArea1, IOArea2 and IOArea3 of
DMANK1. The automatic conversion is enable by programming the General
Configuration Register. The T7904E generates the DMAC(1-0) address bits during
the automatic conversion. Only DMAC(1) is relevant in 16-bit mode. The 8-bit data
bus device must be connected on DMD(15-8). The 16-bit data bus device must be
connected on DMD(23-8).
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