Rev. C - 06 March, 2001
1
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
High Performance 8-bit Microcontrollers
1. Description
Atmel Wireless & Microcontrollers TS80C51Rx2 is high
performance CMOS ROM, OTP, EPROM and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C51Rx2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16/32/64 Kbytes), 256
bytes of internal RAM, a 7-source , 4-level interrupt
system, an on-chip oscilator and three timer/counters.
In addition, the TS80C51Rx2 has a Programmable
Counter Array, an XRAM of 256 or 768 bytes, a
Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication
(EUART) and a X2 speed improvement mechanism.
The fully static design of the TS80C51Rx2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C51Rx2 has 2 software-selectable modes of
reduced
activity
for
further
reduction
in
power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-
bytes)
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Programmable Counter Array with
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
Hardware Watchdog Timer (One-time enabled with
Reset-Out)
2 extra 8-bit I/O ports available on RD2 with high
pin count packages
Asynchronous port reset
Interrupt Structure with
7 Interrupt sources,
4 level priority interrupt system
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
(window), CDIL40 (window), PLCC68, VQFP64
1.4, JLCC68 (window)
2
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
3. Block Diagram
PDIL40
PLCC44
VQFP44 1.4
ROM (bytes)
EPROM (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
I/O
TS80C51RA2
TS80C51RD2
0
0
0
0
256
768
512
1024
32
32
TS83C51RB2
TS83C51RC2
TS83C51RD2
16k
32k
64k
0
0
0
256
256
768
512
512
1024
32
32
32
TS87C51RB2
TS87C51RC2
TS87C51RD2
0
0
0
16k
32k
64k
256
256
768
512
512
1024
32
32
32
PLCC68
VQFP64 1.4
ROM (bytes)
EPROM (bytes)
XRAM (bytes)
TOTAL RAM
(bytes)
I/O
TS80C51RD2
0
0
768
1024
48
TS83C51RD2
64k
0
768
1024
48
TS87C51RD2
0
64k
768
1024
48
Timer 0
INT
RAM
256x8
T0
T1
RxD
TxD
WR
RD
EA/V
PP
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(3)
(3)
C51
CORE
(3) (3)
(3) (3)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
XRAM
256/768x8
IB-bus
PCA
RESET
PROG
Watch
Dog
PCA
ECI
Vss
Vcc
(3)
(3)
(1)
(1): Alternate function of Port 1
(3): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1)
(1)
Port 5
Port 4
P5
P4
(2): Only available on high pin count packages
(2)
(2)
ROM
/EPROM
0/16/32/64Kx8
Rev. C - 06 March, 2001
3
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories:
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P0, P1, P2, P3, P4, P5
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
Power and clock control registers: PCON
HDW Watchdog Timer Reset: WDTRST, WDTPRG
PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi
Interrupt system registers: IE, IP, IPH
Others: AUXR, CKCON
Table 1. All SFRs with their address and their reset value
Bit
addressable
Non Bit addressable
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
CH
0000 0000
CCAP0H
XXXX XXXX
CCAP1H
XXXX XXXX
CCAPL2H
XXXX XXXX
CCAPL3H
XXXX XXXX
CCAPL4H
XXXX XXXX
FFh
F0h
B
0000 0000
F7h
E8h
P5 bit
addressable
1111 1111
CL
0000 0000
CCAP0L
XXXX XXXX
CCAP1L
XXXX XXXX
CCAPL2L
XXXX XXXX
CCAPL3L
XXXX XXXX
CCAPL4L
XXXX XXXX
EFh
E0h
ACC
0000 0000
E7h
D8h
CCON
00X0 0000
CMOD
00XX X000
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
D0h
PSW
0000 0000
D7h
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
C0h
P4 bit
addressable
1111 1111
P5 byte
addressable
1111 1111
C7h
B8h
IP
X000 000
SADEN
0000 0000
BFh
B0h
P3
1111 1111
IPH
X000 0000
B7h
A8h
IE
0000 0000
SADDR
0000 0000
AFh
A0h
P2
1111 1111
AUXR1
XXXX0XX0
WDTRST
XXXX XXXX
WDTPRG
XXXX X000
A7h
98h
SCON
0000 0000
SBUF
XXXX XXXX
9Fh
90h
P1
1111 1111
97h
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
XXXXXX00
CKCON
XXXX XXX0
8Fh
80h
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000
87h
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
reserved
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