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Электронный компонент: U4223B-MFSG3

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U4223B
Rev. A7, 06-Mar-01
1 (18)
Time-Code Receiver with A/D Converter
Description
The U4223B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 kHz to 80 kHz.
The device is designed for radio-controlled clock applications.
Features
D Very low power consumption
D Very high sensitivity
D High selectivity by using two crystal filters
D Power-down mode available
D Only a few external components necessary
D 4-bit digital output
D AGC hold mode
Block Diagram
Power supply
ADC
Decoder
Impulse
circuit
Rectifier &
integrator
AGC
amplifier
PON
CLK D3
D2
D1
D0
DEC
SB
VCC
GND
IN
16
12
17
18
19
20
11
10
9
13
FLB
FLA
SL
4
5
6
14
15
Q1A Q1B Q2A Q2B
REC
INT
1
3
2
7
8
Figure 1. Block diagram
Ordering and Package Information
Extended Type Number
Package
Remarks
U4223B-MFS
SSO20 plastic
U4223B-MFSG3
SSO20 plastic
Taping according to IEC-286-3
T4223B-MF
No
Die on foil
T4223B-MC
No
Die on carrier
U4223B
Rev. A7, 06-Mar-01
2 (18)
Pin Description
3
4
5
13
14
15
16
17
18
19
20
2
1
6
7
8
9
10
12
11
VCC
IN
GND
SB
DEC
D0 (LSB)
D1
D2
D3 (MSB)
PON
CLK
U4223B
Q1A
Q1B
REC
INT
FLA
Q2B
Q2A
SL
FLB
Figure 2. Pinning
Pin
Symbol
Function
1
VCC
Supply voltage
2
IN
Amplifier Input
3
GND
Ground
4
SB
Bandwidth control
5
Q1A
Crystal filter 1
6
Q1B
Crystal filter 1
7
REC
Rectifier output
8
INT
Integrator output
9
DEC
Decoder input
10
FLA
Lowpass filter
11
FLB
Lowpass filter
12
CLK
Clock input for ADC
13
SL
AGC hold mode
14
Q2A
Crystal filter 2
15
Q2B
Crystal filter 2
16
PON
Power ON/OFF control
17
D3
Data out MSB
18
D2
Data out
19
D1
Data out
20
D0
Data out LSB
IN
A ferrite antenna is connected between IN and VCC. For
high sensitivity, the Q factor of the antenna circuit should
be as high as possible. Please note that a high Q factor
requires temperature compensation of the resonant
frequency in most cases. Specifications are valid for
Q>30. An optimal signal-to-noise ratio will be achieved
by a resonant resistance of 50 to 200 k
W.
IN
VCC
Figure 3.
SB
A resistor R
SB
is connected between SB and GND. It
controls the bandwidth of the crystal filters. It is recom-
mended: R
SB
= 0
W for DCF 77.5 kHz, R
SB
= 10 k
W for
60 kHz WWVB and R
SB
= open for JG2AS 40 kHz.
SB
GND
Figure 4.
U4223B
Rev. A7, 06-Mar-01
3 (18)
Q1A, Q1B
In order to achieve a high selectivity, a crystal is con-
nected between the Pins Q1A
and Q1B. It is used with the
serial resonant frequency of the time-code transmitter
(e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS).
The equivalent parallel capacitor of the filter crystal is
internally compensated. The compensated value is about
0.7 pF. If full sensitivity and selectivity are not needed,
the crystal filter can be substituted by a capacitor of 82 pF.
Q1A
Q1B
GND
Figure 5.
REC
Rectifier output and integrator input: The capacitor C
1
between REC and INT is the lowpass filter of the rectifier
and at the same time a damping element of the gain
control.
REC
GND
Figure 6.
DEC
Decoder input: Senses the current through the integration
capacitor C
2
. The dynamic input resistance has a value of
about 420 k
W and is low compared to the impedance of
C
2
.
DEC
GND
Figure 7.
SL
AGC hold mode: SL high (V
SL
= V
CC
) sets normal func-
tion, SL low (V
SL
= 0) disconnects the rectifier and holds
the voltage V
INT
at the integrator output and also the AGC
amplifier gain.
VCC
SL
Figure 8.
INT
Integrator output: The voltage V
INT
is the control voltage
for the AGC. The capacitor C
2
between INT and DEC
defines the time constant of the integrator. The current
through the capacitor is the input signal of the decoder.
INT
GND
Figure 9.
FLA, FLB
Lowpass filter: A capacitor C
3
connected between FLA
and FLB suppresses higher frequencies at the trigger
circuit of the decoder.
FLB
FLB
94 8377
Figure 10.
U4223B
Rev. A7, 06-Mar-01
4 (18)
Q2A, Q2B
According to Q1A/Q1B, a crystal is connected between
the Pins Q2A and Q2B. It is used with the serial resonant
frequency of the time-code transmitter (e.g., 60 kHz
WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equiva-
lent parallel capacitor of the filter crystal is internally
compensated. The value of the compensation is about
0.7 pF.
Q2A
Q2B
GND
Figure 11.
PON
If PON is connected to GND, the receiver will be
activated. The set-up time is typically 0.5 s after applying
GND at this pin. If PON is connected to VCC, the receiver
will switch to power-down mode.
VCC
PON
Figure 12.
D0, D1, D2, D3
The outputs of the ADC consist of PNP-NPN push-pull
stages and can be directly connected to a microcomputer.
In order to avoid any interference of the output into the
antenna circuit, we recommend terminating each digital
output with a capacitor of 10 nF. The digitalized signal of
the ADC is Gray coded (see table). It should be taken into
account that in power-down mode (PON = high), D0, D1,
D2 and D3 will be high.
A sequence of the digitalized time-code signal can be
analyzed by a special noise-suppressing algorithm in
order to increase the sensitivity and the signal-to-noise
ratio (more than 10 dB compared to conventional
decoding). Details about the time-code format are
described separately.
Decimal
Gray
0
0000
1
0001
2
0011
3
0010
4
0110
5
0111
6
0101
7
0100
8
1100
9
1101
10
1111
11
1110
12
1010
13
1011
14
1001
15
1000
VCC
D0 ... D3
GND
PON
Figure 13.
CLK
The input of the ADC is switched to the AGC voltage by
the rising slope of the clock. When conversion time has
passed (about 1.8 ms at 25
C), the digitalized field-
strength signal is stored in the output registers D0 to D3
as long as the clock is high and can be read by a micro-
computer. The falling slope of the clock switches the
input of the ADC to the time-code signal. In the mean-
time, the digitalized time-code signal is stored in the
output registers D0 to D3 as long as the clock is low (see
figure 14).
U4223B
Rev. A7, 06-Mar-01
5 (18)
0
4
8
12
t/ms
50
100
V
clk
mV
7
11
Now, the time-code
signal can be read
Falling edge initiates
time-code conversion
Rising edge initiates
AGC signal conversion
Now, the AGC value can be read
Figure 14.
In order to minimize interferences, we recommend a
voltage swing of about 100 mV. A full supply-voltage
swing is possible but reduces the sensitivity.
CLK
GND
VCC
Figure 15.
Please note:
The signals and voltages at the Pins REC, INT, FLA,
FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by
standard measurement equipment due to very high inter-
nal impedances. For the same reason, the PCB should be
protected against surface humidity.
Design Hints for the Ferrite Antenna
The bar antenna is a very critical device of the complete
clock receiver. Observing some basic RF design rules
helps to avoid possible problems. The IC requires a reso-
nant resistance of 50 k
W to 200 kW. This can be achieved
by a variation of the L/C-relation in the antenna circuit.
It is not easy to measure such high resistances in the RF
region. A more convenient way is to distinguish between
the different bandwidths of the antenna circuit and to cal-
culate the resonant resistance afterwards.
Thus, the first step in designing the antenna circuit is to
measure the bandwidth. Figure 17 shows an example for
the test circuit. The RF signal is coupled into the bar
antenna by inductive means, e.g., a wire loop. It can be
measured by a simple oscilloscope using the 10:1 probe.
The input capacitance of the probe, typically about 10 pF,
should be taken into consideration. By varying the fre-
quency of the signal generator, the resonant frequency
can be determined.
Scope
RF signal
generator
77.5 kHz
C
res
Probe
10 : 1
wire loop
w10 MW
Figure 16.
At the point where the voltage of the RF signal at the
probe drops by 3 dB, the two frequencies can then be
measured. The difference between these two frequencies
is called the bandwidth BW
A
of the antenna circuit. As the
value of the capacitor C
res
in the antenna circuit is known,
it is easy to compute the resonant resistance according to
the following formula:
R
res
+
1
2
p BW
A
C
res
where
R
res
is the resonant resistance,
BW
A
is the measured bandwidth (in Hz)
C
res
is the value of the capacitor in the antenna circuit
(in Farad).
If high inductance values and low capacitor values are
used, the additional parasitic capacitances of the coil
(
v20 pF) must be considered. The Q value of the capa-
citor should be no problem if a high Q type is used. The
Q value of the coil differs more or less from the DC
resistance of the wire. Skin effects can be observed but do
not dominate.
Therefore, it should not be a problem to achieve the
recommended values of the resonant resistance. The use
of thicker wire increases the Q value and accordingly
reduces bandwidth. This is advantageous in order to
improve reception in noisy areas. On the other hand,
temperature compensation of the resonant frequency
might become a problem if the bandwidth of the antenna
circuit is low compared to the temperature variation of the
resonant frequency. Of course, the Q value can also be
reduced by a parallel resistor.