1
Features
Compatible with an Embedded ARM7TDMI
TM
Processor
Programmable Baud Rate Generator
Parity, Framing and Overrun Error Detection
Line Break Generation and Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Multi-drop Mode: Address Detection and Generation
Interrupt Generation
Two Dedicated Peripheral Data Controller Channels Can be Easily Implemented
5-, 6-, 7-, 8- and 9-bit Character Length
Full Scan Testable (up to 98%)
Can be Directly Connected to the Atmel Implementation of the AMBA
TM
Peripheral Bus
(APB)
Description
The two-channel, full-duplex USART features parity, framing and overrun error detec-
tion. A baud rate generator provides the bit period clock named the Baud Rate Clock
to both the receiver and the transmitter. The USART can be programmed to operate in
three different test modes: automatic echo
,
local loopback and remote loopback
.
Two dedicated Peripheral Data Controller channels can be easily implemented. One is
dedicated to the receiver. The other is dedicated to the transmitter.
The generation of interrupts is controlled in the status register by asserting the corre-
sponding interrupt line.
The USART can be used with any 32-bit microcontroller core if the timing diagram
shown on page 8 is respected. When using an ARM7TDMI as the core, the Atmel
Bridge must be used to provide the correct bus interface to the peripheral.
32-bit
Embedded ASIC
Core Peripheral
USART
Rev. 1242E12/01
2
USART
1242E12/01
Figure 1. USART Symbol
p_stb
p_write
p_stb_rising
p_a[13:0]
p_sel_usart
scan_test_mode
usart_int
test_so[2:1]
USART
Functional
Functional
test_se
test_si[2:1]
Test Scan
Test Scan
nreset
p_d_out[31:0]
rxd
USART
clk_ext
txd
USART
rxrdy_to_dma
txrdy_to_dma
clk_txd
en_clk_n
2
2
p_d_in[31:0]
comm_rx
comm_tx
ARM
Core
clock
fdiv1
slow_clock
slclk_eq_sysclk
Power Management
/Clock Controller
PDC
rx_dma_end
tx_dma_end
3
USART
1242E12/01
Table 1. USART Pin Description
Name
Function
Type
Active
Level
Comments
Functional
nreset
Reset System
Input
Low
Resets all the counters and signals
p_a[13:0]
Address Bus
Input
The address takes into account the 2 LSBs
[1:0], but the macrocell does not take these bits
into account (left unconnected).
p_d_in[31:0]
Input Data Bus
Input
From host (bridge)
p_d_out[31:0]
Output Data Bus
Output
To host (bridge)
p_write
Write Enable
Input
High
From host (bridge)
p_stb
Peripheral Strobe
Input
High
From host (bridge)
p_stp_rising
User Interface Clock Signal
Input
From host (bridge). Clock for all DFFs
controlling the configuration registers.
p_sel_usart
Selection of the block
Input
High
From host (bridge)
usart_int
Interrupt signal to AIC
Output
High
Power Management/Clock Controller
clock
System Clock
Input
System clock for the USART output waveforms
fdiv1
USART Clock Enable
Input
System clock (clock) divided
slow_clock
ARM
Core Operation
Input
slclk_eq_sysclk
ARM
Core Operation
Input
ARM
Core
comm_rx
ARM
Core Operation
Input
High
Must be connected to ARM core.
comm_tx
ARM
Core Operation
Input
High
Must be connected to ARM core.
USART
clk_ext
Baud rate signal
Input
From SCK pad
rxd
Receive serial data pin
Input
txd
Transmit serial data pin
Output
rxrdy_to_dma
Output signal to DMA channel
Output
High
Byte available in the Receiver Holding Register
(RHR).
This signal connects to the PDC
(1)
txrdy_to_dma
Output signal to the DMA
channel
Output
High
There are no more characters in the
Transmitter Holding Register (THR).
This signal connects to the PDC
(1)
clk_txd
Output of the baud rate
generator
Output
To SCK pad
en_clk_n
Direction signal for SCK pad
Output
Active in synchronous mode
PDC
rx_dma_end
End of receive DMA transfer
Input
High
Generated by PDC
(1)
tx_dma_end
End of transmit DMA transfer
Input
High
Generated by PDC
(1)
4
USART
1242E12/01
Note:
1. The Peripheral Data Controller (PDC) is a separate block. Please refer to the corresponding datasheet.
Scan Test
Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan out-
puts can be observed. In order to achieve this, the ATPG vectors must be generated on the
entire circuit (top-level), which includes the USART, or all USART I/Os must have a top-level
access and ATPG vectors must be applied to these pins.
Test Scan
scan_test_mode
Must be set when running the
scan vectors
Input
High
test_se
Scan test enable
Input
High/Low
Scan shift/scan capture
test_si[2:1]
Scan test input
Input
High
Entry of scan chain
test_so[2:1]
Scan test output
Output
Output of scan chain
Table 1. USART Pin Description
Name
Function
Type
Active
Level
Comments
5
USART
1242E12/01
Figure 2. USART Block Diagram
Peripheral Data
Controller
(PDC)
When the dedicated Atmel PDC is used, four additional registers are available in the USART
(see page 16). These registers are physically located in the PDC and accessed when select-
ing the USART. For more details concerning these registers, please refer to the PDC
datasheet.
The following pins are exclusively reserved for use with the PDC: rxrdy_to_dma,
txrdy_to_dma, rx_dma_end, tx_dma_end. If the PDC is not used, rx_dma_end and
tx_dma_end must be tied to zero.
Peripheral Data Controller
(PDC)
Receiver
Channel
Transmitter
Channel
Control Logic
Interrupt Control
Baud Rate Generator
Receiver
Transmitter
Atmel Bridge
ASB
APB
usart_int
clock
fdiv1
rxd
txd
sck
USART Channel
Baud Rate Clock
PIO
or Pad
clk_ext
slow_clock
slclk_eq_sysclk
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