Quad Line Receiver
AS10515F16MIL
Austin Semiconductor, Inc.
AS10515F16MIL
Rev. 2.0 11/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
For more products and information
please visit our web site at
www.austinsemiconductor.com
AVAILABLE AS MILITARY
SPECIFICATIONS
Military Equivalent Screening - 883 1.2.2
Quad Line Receiver
PIN ASSIGNMENT
(Top View)
16-Pin FlatPack (F)
GENERAL DESCRIPTION
The AS10515F16MIL is a quad differential amplifier
designed for use in sensing differential signals over long lines.
The base bias supply (V
BB
) is made available at pin 9 to make
the device useful as a Schmitt trigger, or in other applications
where a stable reference voltage is necessary.
Active current sources provide the AS10515F16MIL with
excellent common mode noise rejection. If any amplifier in
a package is not used, one input of that amplifier must be
connected to V
BB
(pin 9) to prevent upsetting the current
source bias network.
P
D
= 150mW Max/Pkg (No Load)
t
pd
= 2.0ns typ
t
r
, t
f
= 2.0ns type (20% - 80%)
FUNCTION
FLATS
BURN-IN
(CONDITION C)
V
CC1
5
GND
A
OUT
6
51
to V
TT
B
OUT
7
51
to V
TT
A
IN
\
8
V
BB
A
IN
9
GND
B
IN
10
GND
B
IN
\
11
V
BB
V
EE
12
V
EE
V
BB
13
V
BB
C
IN
\
14
V
BB
C
IN
15
GND
D
IN
16
GND
D
IN
\
1
V
BB
C
OUT
2
51
to V
TT
D
OUT
3
51
to V
TT
V
CC2
4
GND
PIN ASSIGNMENTS
BURN-IN CONDITIONS:
V
TT
= -2.0V MAX/ -2.2V MIN
V
EE
= -5.7V MAX/ -5.2V MIN
V
BB
= All pins designated for V
BB
must be tied together, no
external voltage applied.
NOTES
1. V
BB
to be used to supply bias to the AS10515F16MIL only and
bypassed (when used) with 0.01 F to 0.1 F capacitor.
2. When the input pin with the bubble goes positive, the output goes
negative.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
D
IN\
C
OUT
D
OUT
V
CC2
V
CC1
A
OUT
B
OUT
A
IN\
D
IN
C
IN
C
IN\
V
BB
V
EE
B
IN\
B
IN
A
IN
LOGIC DIAGRAM
4
5
6
7
10
11
12
13
2
3
14
15
9
V
BB
Quad Line Receiver
AS10515F16MIL
Austin Semiconductor, Inc.
AS10515F16MIL
Rev. 2.0 11/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
NOTES:
1. t
r
= t
f
= 2.0ns 0.2ns measured at (20% - 80%)
2. P
W
> 20ns
3. P
RF
= 1.0 MHz
4. R
1
= 50
resistor in series with 50
coax constituting the 100
load.
5. Unused outputs should be loaded 100
to ground.
6. 2:1 divider may be used.
Figure 1. Switching Test Circuit and Waveforms
D.U.T.
V
CC
= 2.0V 0.005V
25 F
20%
0.1 F
20%
Coax A
Channel A
Channel B
Coax B
R
1
C
L
Coax
*Pulse
Generator
Input
0.1 F 20%
V
EE
= -3.2V 0.005V
*Pulse Generator must be capable of
rise and fall times of 2.0ns 0.2ns.
R
1
= 50
resistor in series with
a 50
coax cable constituting
the 100
load.
t
r
t
f
80%
50%
20%
80%
50%
20%
80%
50%
20%
80%
50%
20%
80%
50%
20%
80%
50%
20%
> 20ns
V
IN
V
OUT
V
OUT
\
t
TLH
t
PLH
t
PHL
t
THL
t
THL
t
TLH
t
PLH
t
PHL
PS1
PS2
Quad Line R
ecei
v
e
r
AS10515F16MIL
Austin Semiconductor, Inc.
AS10515F16MIL
Rev. 2.0 11/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
* ELECTRICAL CHARACTERISTICS
Each MECL 10K series circuit has been designed to meet
the dc specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs
are terminated through a 100
resistor to -2.0 volts.
QUIESCENT LIMIT TABLE*
** Connected to pin 9.
*** Measure voltage on pin 9 while it is connected to other pins.
V
IH1
V
IL1
V
IH2
V
IL2
P
S1
P
S2
V
EEL
V
EE
V
CB
T
A
= 25C
-0.78
-1.85
-1.105 -1.475
+1.11
+0.31
-3.2
-5.2
-5.2
T
A
= 125C
-0.63
-1.82
-1.000 -1.400
+1.24
+0.36
-3.2
-5.2
-5.2
T
A
= -55C
-0.88
-1.92
-1.255 -1.510
+1.01
+0.28
-3.2
-5.2
-5.2
Test Voltage Values (Volts)
Test
Temperature
SYMBOL PARAMETER
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
V
IH1
V
IL1
V
IH2
V
IL2
V
EE
V
CC
***
P.U.T.
V
OH
High Output
Voltage
-0.93
-0.78 -0.825 -0.63
-1.08
-0.88
V
5, 6, 11, 12 4, 7, 10, 13
8
1, 16
4 - 7
11 - 13
2, 3 ,14, 15
V
OL
Low Output
Voltage
-1.85
-1.62
-1.82 -1.545 -1.92 -1.655
V
4, 7, 10, 13 5, 6, 11, 12
8
1, 16
4 - 7
11 - 13
2, 3 ,14, 15
V
OH1
High Output
Voltage
-0.95
-0.78 -0.845 -0.63
-1.10
-0.88
V
5, 6, 11, 12 4, 7, 10, 13
8
1, 16
4 - 7
11 - 13
2, 3 ,14, 15
V
OL1
Low Output
Voltage
-1.85
-1.60
-1.82 -1.525 -1.92 -1.635
V
4, 7, 10, 13 5, 6, 11, 12
8
1, 16
4 - 7
11 - 13
2, 3 ,14, 15
**V
BB
Reference
Voltage
-1.35
-1.23
-1.24
-1.12
-1.44
-1.32
V
8
1, 16
5, 6
11, 12
9
I
EE
Power Supply
Current
-26
-29
-29
mA
8
1, 16
5, 6
11, 12
8
I
IH
Input Current
High
95
165
165
A
4 - 7
10 - 13
8
1, 16
4 - 7
10 - 13
I
CBO
Input Leakage
Current
-1.0
-1.0
-1.5
A
8
1, 16
4 - 7
10 - 13
4 - 7
10 - 13
LIMITS
TEST VOLTAGE APPLIED TO PINS BELOW:
Pinouts referenced are for F package, check Pin Assignments
V
CC
= 0V, Output Load = 100
to -2.0V
Subgroup 3
Functional
Parameters:
+25C
Subgroup 1
+125C
Subgroup 2
-55C
Quad Line R
ecei
v
e
r
AS10515F16MIL
Austin Semiconductor, Inc.
AS10515F16MIL
Rev. 2.0 11/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
* ELECTRICAL CHARACTERISTICS
Each MECL 10K series circuit has been designed to meet
the dc specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse
air flow greater than 500 linear fpm is maintained. Outputs
are terminated through a 100
resistor to -2.0 volts.
QUIESCENT LIMIT TABLE*
V
IH1
V
IL1
V
IH2
V
IL2
P
S1
P
S2
V
EEL
V
EE
V
CB
T
A
= 25C
-0.78
-1.85
-1.105 -1.475
+1.11
+0.31
-3.2
-5.2
-5.2
T
A
= 125C
-0.63
-1.82
-1.000 -1.400
+1.24
+0.36
-3.2
-5.2
-5.2
T
A
= -55C
-0.88
-1.92
-1.255 -1.510
+1.01
+0.28
-3.2
-5.2
-5.2
Test Voltage Values (Volts)
Test
Temperature
SYMBOL
PARAMETER
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
V
IN
V
OUT
V
CC
V
EEL
P.U.T.
t
TLH
Rise Time
1.1
3.3
1.0
4.4
1.0
3.9
ns
4, 7, 11, 13 2, 3, 14, 15
1, 16
8
2, 3 ,14, 15
t
THL
Fall Time
1.1
3.3
1.0
4.4
1.0
3.9
ns
4, 7, 11, 13 2, 3, 14, 15
1, 16
8
2, 3 ,14, 15
t
PHL
Propagation Delay
High to Low
1.0
2.9
1.0
4.0
1.0
3.5
ns
4, 7, 11, 13 2, 3, 14, 15
1, 16
8
2, 3 ,14, 15
t
PLH
Propagation Delay
Low to High
1.0
2.90
1.0
4.0
1.0
3.5
ns
4, 7, 11, 13 2, 3, 14, 15
1, 16
8
2, 3 ,14, 15
Functional
Parameters:
+25C
Subgroup 9
LIMITS
TEST VOLTAGE APPLIED TO PINS BELOW:
Pinouts referenced are for F package, check Pin Assignments
V
CC
= 2.0V, Output Load = 100
to GND
Subgroup 11
+125C
Subgroup 10
-55C
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