FLASH

AS29F010

Austin Semiconductor, Inc.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

AS29F010
Rev. 0.3 10/02

128K x 8 FLASH

UNIFORM SECTOR 5.0V FLASH MEMORY

AVAILABLE AS MILITARY
SPECIFICATIONS

· MIL-STD-883
· SMD 5962-96690

FEATURES

· Single 5.0V ±10% power supply operation
· Low power consumption:

12 mA typical active read current

30 mA typical program/erase current

<1 µA typical standby current

· Flexible sector architecture

Eight 16Kbyte sectors

Any combination of sectors can be erased

Full chip erase

· Sector protection

Hardware-based feature that disables/reenables program

and erase operations in any combination of sectors

Sector protection/unprotection can be implemented

using standard PROM programming equipment

· Embedded Algorithms

Embedded Erase algorithm automatically pre-programs

and erases the chip or any combination of designated
sectors

Embedded Program algorithm automatically programs

and verifies data at specified address

· Erase Suspend/Resume

Supports reading data from a sector not being erased

· Minimum 1 million erase cycles guaranteed per sector
· Compatible with JEDEC standards

Pinout and software compatible with single-power-

supply FLASH

Superior inadvertent write protection

· Data\ Polling and Toggle Bits

Provides a software method of detecting program or

erase cycle completion

OPTIONS

MARKING

· Timing

50ns*

-5

60ns

-6

70ns

-7

90ns

-9

120ns

-12

150ns

-15

· Package

Ceramic DIP (600 mil)

· Temperature

Industrial Temperature (-40°C to +85°C) IT
Military Temperature (-55°C to +125°C) XT
883C Processing (-55°C to +125°C)

883C

QML Processing (-55°C to +125°C)

NOTES:

*50ns (-5) option available with IT, XT, and 883C options

only.

For more products and information

please visit our web site at

www.austinsemiconductor.com

PIN ASSIGNMENT

(Top View)

32-PIN Ceramic DIP (CW)

A16
A15
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

WE\
NC
A14
A13
A8
A9
A11
OE\
A10
CE\
DQ7
DQ6
DQ5
DQ4
DQ3

1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6

3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7

FLASH

AS29F010

Austin Semiconductor, Inc.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

AS29F010
Rev. 0.3 10/02

GENERAL DESCRIPTION

The AS29F010 is a 1Mbit, 5.0 Volt-only FLASH memory

organized as 131,072 bytes. The AS29F010 is offered in a 32-pin
CDIP package. The byte-wide data appears on DQ0-DQ7. The
device is designed to be programmed in-system with the
standard system 5.0 Volt V

supply. A 12.0 volt V

is not

required for program or erase operations. The device can also
be programmed or erased in standard EPROM programmers.

This device is manufactured using 0.32 µm process

technology. It is available with access times of 50, 60, 70, 90,
120, and 150ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (CE\), write enable (WE\), and
output enable (OE\) controls.

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.

The device is entirely command set compatible with the

JEDEC single-power-supply FLASH standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other FLASH or EPROM
devices.

Device programming occurs by executing the program

command sequence. This invokes the Embedded Program
algorithm -- an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command

sequence. This invokes the Embedded Erase algorithm -- an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data\Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or accept
another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents
of other sectors. The device is erased when shipped from the
factory.

The hardware data protection measures include a low V

detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory, and is implemented
using standard EPROM programmers.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode. The
device electrically erases all bits within a sector simultaneously
via Fowler-Nordheim tunneling. The bytes are programmed
one byte at a time using the EPROM programming mechanism
of hot electron injection.

PIN CONFIGURATION

PIN

DESCRIPTION

A0 - A16

17 Addresses

DQ0 - DQ7 8 Data Inputs/Outputs

CE\

Chip Enable

OE\

Output Enable

WE\

Write Enable

+5 Vold Single Power Supply

Device Ground

No Connect

LOGIC SYMBOL

FLASH

AS29F010

Austin Semiconductor, Inc.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

AS29F010
Rev. 0.3 10/02

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the
device. The appropriate device bus operations table lists the
inputs and control levels required, and the resulting output.
The following subsections describe each of these operations
in further detail.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE\ and OE\ pins to V

. CE\ is the power control and

selects the device. OE\ is the output control and gates array
data to the output pins. WE\ should remain at V

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.

See "Reading Array Data" for more information. Refer to

the AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing waveforms.
ICC1 in the DC Characteristics table represents the active
current specification for reading array data.

TABLE 1: DEVICE BUS OPERATIONS

OPERATION

CE\

OE\

WE\

Addresses

DQ0 - DQ7

Read

OUT

Write

Standby

± 0.5V

High-Z

Output Disable

High-Z

Hardware Reset

High-Z

NOTES:

1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the "Sector Protection/
Unprotection" section.

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of memory),
the system must drive WE\ and CE\ to V

, and OE\ to V

An erase operation can erase one sector, multiple sectors,

or the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A "sector address"
consists of the address bits required to uniquely select a
sector. See the "Command Definitions" section for details on
erasing a sector or the entire chip.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ7 - DQ0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for more
information.

CC2

in the DC Characteristics table represents the active

current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits on
DQ7 - DQ0. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section in the
appropriate data sheet for timing diagrams.

FLASH

AS29F010

Austin Semiconductor, Inc.

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

AS29F010
Rev. 0.3 10/02

Standby Mode

When the system is not reading or writing to the device, it

can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.

The device enters the CMOS standby mode when the CE\

pin is held at V

± 0.5V. (Note that this is a more restricted

voltage range than V

.) The device enters the TTL standby

more when CE\ is held at V

. The device requires the standard

access time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is completed.

CC3

in the DC Characteristics table represents the standby

current specification.

Output Disable Mode

When the OE\ input is at V

, output from the device is

disabled. The output pins are placed in the high impedance
state.

Autoselect Mode

The autoselect mode provides manufacturer and device

identification, and sector protection verification, through
identifier codes output on DQ7 - DQ0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.

When using programming equipment, the autoselect mode

requires V

on address pin A9. Address pins A6, A1, and A0

must be as shown in the Autoselect Codes (High Voltage
Method) table. In addition, when verifying sector protection,
the sector address must appear on the appropriate highest
order address bits. Refer to the corresponding Sector Address
Tables. The Command Definitions table shows the remaining

SECTOR

A16

A15

A14

ADDRESS RANGE

SA0

00000h - 03FFFh

SA1

04000h - 07FFFh

SA2

08000h - 0BFFFh

SA3

0C000h - 0FFFFh

SA4

10000h - 13FFFh

SA5

14000h - 17FFFh

SA6

18000h - 1BFFFh

SA7

1C000h - 1FFFFh

TABLE 2: SECTOR ADDRESSES TABLE

NOTE:

All sectors are 16 Kbytes in size.

address bits that are don't care. When all necessary bits have
been set as required, the programming equipment may then
read the corresponding identifier code on DQ7 - DQ0

To access the autoselect codes in-system, the host system

can issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
not require V

. See "Command Definitions" for details on

using the autoselect mode.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.

Sector protection/unprotection must be implemented

using programming equipment. The procedure requires a high
voltage (V

) on address pin A9 and the control pins. The

device is shipped with all sectors unprotected. It is possible to
determine whether a sector is protected or unprotected. See
"Autoselect Mode" for details.

Hardware Data Protection

The command sequence requirement of unlock cycles for

programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V

power-up and power-down transitions, or from system

noise.

Low V

Write Inhibit

When V

is less than V

LKO

, the device does not accept

any write cycles. This protects data during V

power-up and

power-down. The command register and all internal program/

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