DRAM
DRAM
DRAM
DRAM
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
AS4LC4M16
Rev. 1.0 7/02
4 MEG x 16 DRAM
Extended Data Out (EDO) DRAM
FEATURES
Single +3.3V 0.3V power supply.
Industry-standard x16 pinout, timing, functions, and
package.
12 row, 10 column addresses
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compatible
Extended Data-Out (EDO) PAGE MODE access
4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH
distributed across 64ms
Optional self refresh (S) for low-power data retention
Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020
OPTIONS
MARKINGS
Package(s)
50-pin TSOP (400-mil)
DG
Timing
50ns access
-5
60ns access
-6
Refresh Rates
Standard Refresh
None
Self Refresh
S*
Operating Temperature Ranges
Military (-55C to +125C)
XT
Industrial (-40C to +85C)
IT
NOTE:
The \ symbol indicates signal is active LOW.
*Contact factory for availability. Self refresh option available on IT
version only.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
50-Pin TSOP (DG)
Configuration
4 Meg x 16
Refresh
4K
Row Address
A0-A11
Column Addressing
A0-A9
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-5
84ns
50ns
20ns
25ns
13ns
8ns
-6
104ns 60ns
25ns
30ns
15ns
10ns
KEY TIMING PARAMETERS
DRAM
DRAM
DRAM
DRAM
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AS4LC4M16
Rev. 1.0 7/02
FUNCTIONAL BLOCK DIAGRAM
DRAM
DRAM
DRAM
DRAM
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AS4LC4M16
Rev. 1.0 7/02
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic
random-access memory device containing 67,108,864 bits and
designed to operate from 3V to 3.6V. The device is functionally
organized as 4,194,304 locations containing 16 bits each. The
4,194,304 memory locations are arranged in 4,096 rows by 1,024
columns. During READ or WRITE cycles, each location is
uniquely addresses via the address bits: 12 row-address bits
(A0 - A11) and 10 column-address bits (A0 - A9). In addition,
both byte and word accesses are supported via the two CAS\
pins (CASL\ and CASH\).
The CAS\ functionality and timing related to address and
control functions (e.g., latching column addresses or selecting
CBR REFRESH) is such that the internal CAS\ signal is
determined by the first external CAS\ signal (CASL\ or CASH\)
to transition LOW and the last to transition back HIGH. The
CAS\ functionality and timing related to driving or latching data
is such that each CAS\ signal independently controls the
associated either DQ pins.
The row address is latched by the RAS\ signal, then the
column address is latched by CAS\. This device provides
EDO-PAGE-MODE operation, allowing for fast successive data
operations (READ, WRITE or READ-MODIFY-WRITE) within
a given row.
The 4 Meg x 16 DRAM must be refreshed periodically in
order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable, as
mentioned in the General Description. Use of both CAS\
signals resulted in a word access via the 16 I/O pins
(DQ0 - DQ15). Using only one of the two signals results in a
BYTE access cycle. CASL\ transitioning LOW selects an
access cycle for the lower byte (DQ0 - DQ7), and CASH\
transitioning LOW selects an access cycle for the upper byte
(DQ8-DQ15). General byte and word access timing is shown in
Figures 1 and 2.
FIGURE 1: WORD and BYTE WRITE Example
DRAM
DRAM
DRAM
DRAM
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AS4LC4M16
Rev. 1.0 7/02
DRAM ACCESS (continued)
A logic HIGH on WE\ dictates read mode, while a logic
LOW on WE\ dictates write mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS\ (CASL\
or CASH\), whichever occurs last. An EARLY WRITE occurs
when WE is taken LOW prior to either CAS\ falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE falls after
CAS\ (CASL\ or CASH\) is taken LOW. During EARLY WRITE
cycles, the data outputs (Q) will remain High-Z, regardless of
the state of OE\. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE\ must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE\ LOW,
no write will occur, and the data outputs will drive read data
from the accessed location.
Additionally, both bytes are active. A CAS\ precharge
must be satisfied prior to changing modes of operation be-
tween the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte are
not allowed during the same cycle. However, an EARLY WRITE
on one byte and a LATE WRITE on the other byte, after a CAS\
precharge has been satisfied, are permissible.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output
buffers off (High-Z) with the rising edge of CAS\. If CAS\ went
HIGH and OE\ was LOW (active), the output buffers would be
disabled. The 64MB EDO DRAM offers an accelerated page
mode cycle by eliminating output disable from CAS\ HIGH.
This option is called EDO, and it allows CAS\ precharge time
(t
CP
) to occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS\ goes HIGH,
as long as RAS\ and OE\ are held LOW and WE\ is held HIGH.
OE\ can be brought LOW or HIGH while CAS\ and RAS\ are
LOW, and the DQs will transition between valid data and High-
Z. Using OE\, there are two methods to disable the outputs and
FIGURE 2: WORD and BYTE READ Example
DRAM
DRAM
DRAM
DRAM
DRAM
AS4LC4M16
Austin Semiconductor, Inc.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AS4LC4M16
Rev. 1.0 7/02
FIGURE 3: OE\ Control of DQs
FIGURE 4: WE\ Control of DQs
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