2-73
AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
DRAM
AVAILABLE IN MILITARY
SPECIFICATIONS
MIL-STD-883
SMD Planned
FEATURES
Industry-standard x4 pinout, timing, functions and
packages
High-performance CMOS silicon-gate process
Single +3.3V
0.3V power supply
Low power, 1mW standby; 150mW active, typical
All inputs, outputs and clocks are TTL-compatible
Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-
?
R
?
A
/
S (CBR)
HIDDEN
2,048-cycle (11 row-, 11 column-addresses)
Extended Data-Out (EDO) PAGE access cycle
5V-tolerant I/Os (5.5V maximum V
IH
level)
OPTIONS
MARKING
Timing
60ns access (Contact Factory)
-6
70ns acess
-7
80ns access
-8
Packages
Ceramic SOJ
ECJ
No. 505
Ceramic LCC
EC
No. 212
Ceramic Gull Wing
ECG
No. 603
PIN ASSIGNMENT (Top View)
24/28-Pin
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
A logic HIGH on
?
W
/
E dictates READ mode while a logic
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of
?
W
/
E or
/
C
/
A
/
S,
whichever occurs last. An EARLY WRITE occurs when
?
W
/
E is taken LOW prior to
/
C
/
A
/
S falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when
?
W
/
E falls after
/
C
/
A
/
S
was taken LOW. During EARLY WRITE cycles, the data-
outputs (Q) will remain High-Z regardless of the state of
?
O
/
E. During LATE WRITE or READ-MODIFY-WRITE cycles,
?
O
/
E must be taken HIGH to disable the data-outputs prior to
applying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping
?
O
/
E LOW, no write will
occur, and the data-outputs will drive read data from the
accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by
?
W
/
E and
?
O
/
E.
FAST PAGE MODE
FAST PAGE operations allow faster data operations
(READ, WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The FAST PAGE cycle is
always initiated with a row-address strobed-in by
?
R
?
A
/
S
followed by a column-address strobed-in by
?C?A/S. ?C?A/S may
be toggled-in by holding
?
R
?
A
/
S LOW and strobing-in differ-
ent column-addresses, thus executing faster memory cycles.
Returning
R?A/S HIGH terminates the FAST PAGE MODE
of operation.
4 MEG x 4 DRAM
3.3V, EDO PAGE MODE
V
CC
DQ1
DQ2
/
W
/
E
/
R
/
A
/
S
NC
A10
A0
A1
A2
A3
V
CC
V
SS
DQ4
DQ3
/
C
/
A
/
S
/
O
/
E
A9
A8
A7
A6
A5
A4
Vss
1
2
3
4
5
6
9
10
11
12
13
14
28
27
26
25
24
23
20
19
18
17
16
15
GENERAL DESCRIPTION
The AS4LC4M4 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. The AS4LC4M4
?
R
?
A
/
S is used to latch the first 11
bits and
?
C
?
A
/
S the latter 11 bits. READ and WRITE cycles are
selected with the
?W/E input. A logic HIGH on
?
W
/
E dictates READ mode while a logic LOW on
?
W
/
E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of
?W/E or ?C?A/S, whichever occurs last. If
?
W
/
E goes LOW prior to
?
C
?
A
/
S going LOW, the output pins
remain open (High- Z) until the next
?
C
?
A
/
S cycle, regardless
of
?
O
/
E.
KEY TIMING PARAMETERS
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-6
110ns
60ns
30ns
30ns
15ns
12ns
-7
130ns
70ns
35ns
35ns
18ns
15ns
-8
150ns
80ns
40ns
40ns
20ns
20ns
2-74
AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
?
R
?
A
/
S and
?
C
?
A
/
S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If
?
O
/
E is toggled or
pulsed after
?
C
?
A
/
S goes HIGH while
?
R
?
A
/
S remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
?
W
/
E can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR'd,
?
O
/
E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing
?
W
/
E to the idle banks during
?
C
?
A
/
S high time
will also High-Z the outputs. Independent of
?
O
/
E control,
the outputs will disable after
t
OFF, which is referenced
from the rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
EDO PAGE MODE
The AS4LC4M4E8 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?
C
?
A
/
S returns HIGH. EDO allows
?
C
?
A
/
S precharge time (
t
CP)
to occur without the output data going invalid. This elimi-
nation of
?
C
?
A
/
S output control allows pipeline READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO-PAGE-MODE DRAMs operate similarly to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after
?
C
?
A
/
S goes HIGH during READs,
provided
?
R
?
A
/
S and
?
O
/
E are held LOW. If
?
O
/
E is pulsed while
,,
,,,
V
V
IH
IL
CAS
V
V
IH
IL
RAS
V
V
IH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,,
COLUMN (B)
,
,,,,
,,
V
V
IH
IL
OE
V
V
IOH
IOL
OPEN
DQ
tOD
VALID DATA (B)
VALID DATA (A)
,
COLUMN (C)
,,,
,,,
VALID DATA (A)
tOE
,,
VALID DATA (C)
,
COLUMN (D)
,,,
,,
,
VALID DATA (D)
tOD
tOEHC
tOD
tOEP
tOES
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS cycle
if
t
OEP is met.
Figure 1
OUTPUT ENABLE AND DISABLE
2-75
AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
REFRESH
Preserve correct memory cell data by maintaining power and executing a
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
A
/
S refresh cycle
(
?
R
?
A
/
S ONLY, CBR, or HIDDEN) so that all 2,048 combinations of
?
R
?
A
/
S addresses are executed at least every 32ms, regardless
of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic
?
R
?
A
/
S addressing.
,,
,,
V
V
IH
IL
CAS
V
V
IH
IL
RAS
V
V
IH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,
DON'T CARE
UNDEFINED
,
,,
,,
,,
V
V
IH
IL
WE
V
V
IOH
IOL
OPEN
DQ
,
,
,
,,,
,
,,
,,
,,
,,
tWPZ
The DQs go to High-Z if WE falls, and if
t
WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
V
V
IH
IL
OE
,
,
VALID DATA (B)
t
WHZ
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
t
WHZ
COLUMN (D)
,,
,,,
,,,
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
Figure 2
??
??
?
W
//
//
/
E CONTROL OF DQs
2-76
AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
FUNCTIONAL BLOCK DIAGRAM
2048
2048
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
11
11
11
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
V
DD
Vss
11
WE
CAS
10
COLUMN-
ADDRESS
BUFFER(11)
ROW-
ADDRESS
BUFFERS (11)
2048
ROW
DECODER
2048
1024
COLUMN
DECODER
OE
DQ1
DQ2
DQ3
DQ4
4
4
4
4
REFRESH
COUNTER
1
ROW TRANSFER
(1 OF 2)
ROW TRANSFER
(1 OF 2)
1024
4096 x 1024 x 4
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
DATA-IN
BUFFER
COMPLEMENT
SELECT
2048
ROW SELECT
(2 of 4096)
TRUTH TABLE
ADDRESSES
DATA-IN/OUT
FUNCTION
?
R
?
A
/
S
?
C
?
A
/
S
?
W
/
E
?
O
/
E
t
R
t
C
DQ1-DQ4
Standby
H
H
>
X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H
>
L
L
>
H
ROW
COL
Data-Out, Data-In
EDO-PAGE-MODE
1st Cycle
L
H
>
L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H
>
L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H
>
L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H
>
L
L
X
n/a
COL
Data-In
Any Cycle
L
L
>
H
H
L
n/a
n/a
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H
>
L
H
>
L
L
>
H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H
>
L
H
>
L
L
>
H
n/a
COL
Data-Out, Data-In
HIDDEN
READ
L
>
H
>
L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L
>
H
>
L
L
L
X
ROW
COL
Data-In
?
R
?
A
/
S-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
CBR REFRESH
H
>
L
L
H
X
X
X
High-Z
2-77
AS4LC4M4
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
Rev. 11/97
DS000022
AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
pin Relative to V
SS
................. -1V to +4.6V
Voltage on NC, Inputs or I/O pins
Relative to V
SS
.................................................... -1V to +5.5V
Operating Temperature, T
A
(ambient) .. TA(MIN) = -55
C
................................................................... TC (MAX) = 125
C
Storage Temperature ................................... -55
C to +150
C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (V
CC
= +3.3V
0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
Supply Voltage
V
CC
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
V
IH
2.0
VCC+1
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
V
IL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
Any input 0V
V
IN
5.5V Vcc = 3.6V
I
I
-2
2
A
(All other pins not under test = 0V) (NC pins not tested)
OUTPUT LEAKAGE CURRENT (Q is disabled; 0V
V
OUT
5.5V) Vcc=3.6V
I
OZ
-10
10
A
OUTPUT LEVELS
V
OH
2.4
V
Output High Voltage (I
OUT
= -2mA)
Output Low Voltage (I
OUT
= 2mA)
V
OL
0.4
V
PARAMETER/CONDITION
SYM
-6
-7
-8
UNITS
NOTES
STANDBY CURRENT: (TTL)
I
CC
1
2
2
2
mA
(
?
R
?
A
/
S =
?
C
?
A
/
S = V
IH
)
STANDBY CURRENT: (CMOS)
I
CC
2
1
1
1
mA
(
?
R
?
A
/
S =
?
C
?
A
/
S = other inputs = V
CC
-0.2V
OPERATING CURRENT: Random READ/WRITE
Average power supply current
I
CC
3
120
110
100
mA
3, 4, 12
(
?
R
?
A
/
S,
?
C
?
A
/
S, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
I
CC
4
110
100
90
mA
3, 4, 12
(
?
R
?
A
/
S = V
IL
,
?
C
?
A
/
S, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT:
?
R
?
A
/
S ONLY
Average power supply current
I
CC
5
120
110
100
mA
3, 12
(
?
R
?
A
/
S cycling,
?
C
?
A
/
S = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
Average power supply current
I
CC
6
120
110
100
mA
3, 5
(
?
R
?
A
/
S,
?
C
?
A
/
S, address cycling:
t
RC =
t
RC [MIN])
MAX
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