SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

128K x 36 SSRAM

SYNCHRONOUS ZBL SRAM
FLOW-THRU OUTPUT

FEATURES

· High frequency and 100% bus utilization
· Fast cycle times: 11ns & 12ns

· Single +3.3V +5% power supply (V

)

· Advanced control logic for minimum control signal interface
· Individual BYTE WRITE controls may be tied LOW
· Single R/W\ (READ/WRITE) control pin
· CKE\ pin to enable clock and suspend operations
· Three chip enables for simple depth expansion
· Clock-controlled and registered addresses, data I/Os and
control signals
· Internally self-timed, fully coherent WRITE
· Internally self-timed, registered outputs to eliminate the
need to control OE\
· SNOOZE MODE for reduced-power standby
· Common data inputs and data outputs
· Linear or Interleaved Burst Modes
· Burst feature (optional)
· Pin/function compatibility with 2Mb, 8Mb, and 16Mb ZBL
SRAM
· Automatic power-down

OPTIONS

MARKING

· Timing (Access/Cycle/MHz)

8.5ns/11ns/90 MHz

-11

9ns/12ns/83 MHz

-12

· Packages

100-pin TQFP

DQ No. 1001

· Operating Temperature Ranges

Military (-55

C to +125

Industrial (-40

C to +85

GENERAL DESCRIPTION

The Austin Semiconductor, Inc. Zero Bus Latency SRAM

family employs high-speed, low-power CMOS designs using an ad-
vanced CMOS process.

ASI's 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core

with advanced synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMS are optimized for 100 percent bus utilization,
eliminating any turnaround cycles for READ to WRITE, or WRITE
to READ, transitions. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input (CLK). The
synchronous inputs include all addresses, all data inputs, chip enable
(CE\), two additional chip enables for easy depth expansion (CE2,
CE2\), cycle start input (ADV/LD\), synchronous clock enable (CKE\),
byte write enables (BWa\, BWb\, BWc\, and BWd\) and read/write (R/
W\).

Asynchronous inputs include the output enable (OE\, which

may be tied LOW for control signal minimization), clock (CLK) and
snooze enable (ZZ, which may be tied LOW if unused). There is also
a burst mode pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left unconnected if
burst is unused. The flow-through data-out (Q) is enabled by OE\.
WRITE cycles can be from one to four bytes wide as controlled by the
write control inputs.

All READ, WRITE and DESELECT cycles are initiated by

the ADV/LD\ input. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV/LD\). Use of
burst mode is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.

To allow for continuous, 100 percent use of the data bus,

the flow-through ZBL SRAM uses a LATE WRITE cycle. For ex-
ample, if a WRITE cycle begins in clock cycle one, the address is
present on rising edge one. BYTE WRITEs need to be asserted on the
same cycle as the address. The write data associated with the address
is required one cycle later, or on the rising edge of clock cycle two.

Address and write control are registered on-chip to simplify

WRITE cycles. This allows self-timed WRITE cycles. Individual
byte enables allow individual bytes to be written. During a BYTE
WRITE cycle, BWa\ controls DQa pins; BWb\ controls DQb pins;
BWc\ controls DQc pins; and BWd\ controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e., when ADV/LD\ is
LOW. Parity/ECC bits are available on this device.

Austin's 4Mb ZBL SRAMs operate from a +3.3V V

power supply, and all inputs and outputs are LVTTL-compatible.
The device is ideally suited for systems requiring high bandwidth and
zero bus turnaround delays.

For more products and information

please visit our web site at

www.austinsemiconductor.com

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

PIN ASSIGNMENT

(Top View)

100-pin TQFP (DQ)

PIN DESCRIPTIONS

TQFP PINS

SYMBOL

TYPE

DESCRIPTION

32-35, 44-50,

81, 82, 99, 100

SA0

SA1

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup

and hold times around the rising edge of CLK. Pins 83 and 84 are reserved as

address bits for the higher-density 8Mb and 16Mb ZBL SRAMs, respectively. SA0 and

SA1 are the two least significant bits (LSB) of the address field and set the internal

burst counter if burst is desired.

BWa\

BWb\

BWc\

BWd\

Input

Synchronous Byte Write Enables:

These active LOW inputs allow individual bytes to

be written when a WRITE cycle is active and must meet the setup and hold times

around the rising edge of CLK.

BYTE WRITEs need to be asserted on the same cycle

as the address.

BWa\ controls DQa pins; BWb\ controls DQb pins; BWc\ controls

DQc pins; BWd\ controls DQd pins.

CKE\

Input

Synchronous

Clock

Enable:

This

active

LOW

input

permits

CLK

propagate

throughout the device.

When CKE is HIGH, the device ignores the CLK input and

effectively internally extends the previous CLK cycle.

This input must meet setup and

hold times around the rising edge of CLK.

R/W\

Input

Read/Write:

This input determines the cycle type when ADV/LD\ is LOW and is the

only means for determining READs and WRITEs.

READ cycles may not be converted

into WRITEs (and vice versa) other than by loading a new address.

A LOW on this pin

permits BYTE WRITE operations and must meet the setup and hold times around the

rising edge of CLK. Full bus-width WRITEs occur if all byte write enables are LOW.

1
2
3
4
5
6
7
8

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71

65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQc
DQc
DQc

DQc
DQc
DQc
DQc

DQc
DQc

DQd

DQd
DQd
DQd
DQd

DQd
DQd

DQd

DQb
DQb
DQb
V

DQb
DQb
DQb
DQb
V

DQb
DQb
V

ZZ
DQa
DQa
V

DQa
DQa
DQa
DQa
V

DQa
DQa
DQa

MODE (LBO\)

SA1

SA0

DNU

CE\

CE2

BWd\

BWc\

BWb\

BWa\

CE2\

CLK

R/W\

CKE\

OE\ (G\)

ADV/LD\

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

PIN DESCRIPTIONS (continued)

TQFP PINS

SYMBOL

TYPE

DESCRIPTION

Input

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a

low-power standby mode in which all data in the memory array is retained. When ZZ

is active, all other inputs are ignored.

CLK

Input

Clock:

This signal registers the address, data, chip enables, byte write enables and

burst control inputs on its rising edge.

All synchronous inputs must meet setup and

hold times around the clock's rising edge.

98, 92

CE\, CE2\

Input

Synchronous Chip Enable:

These active LOW inputs are used to enable the device

and are sampled only when a new external address is loaded (ADV/LD\ LOW).

CE2\

can be used for memory depth expansion.

CE2

Input

Synchronous Enable:

This active

HIGH input

used

to enable

the device

and is

sampled only when a new external address is loaded (ADV/LD\ LOW).

This input can

be used for memory depth expansion.

OE\

(G\)

Input

Output Enable: This active LOW, asynchronous inputs enables the data I/O output

drivers. G\ is the JEDEC-standard term for OE\.

ADV/LD\

Input

Synchronous Address Advance/Load:

When HIGH, this input is used to advance the

internal burst counter, controlling burst access after the external address is loaded.

When ADV/LD\ is HIGH, R/W\ is ignored.

A LOW on ADV/LD\ clocks a new address

at the CLK rising edge.

MODE

(LBO\)

Input

Mode:

This inputs selects the burst sequence.

A LOW on this pin selects linear burst.

NC or HIGH on this pin selects interleaved burst.

Do not alter input state while device

is operating. LBO\ is the JEDEC-standard term for MODE.

(a) 51, 52, 53, 56-59,

62, 63

(b) 68, 69, 72-75, 78,

79, 80

(d) 18, 19, 22-25, 28,

29, 30

DQa

DQb

DQc

DQd

Input/Output

SRAM Data I/Os:

Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is DQc pins;

Byte "d" is DQd pins.

Input data must meet setup and hold times around the rising

edge CLK.

15, 16, 41, 65, 91

Supply

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

5, 10, 14, 17, 21, 26

40, 55, 60, 66, 67, 71

76, 90

Vss

Ground

Ground: GND

4, 11, 20, 27, 54, 61

70, 77

Supply

Isolated

Output

Buffer

Supply:

See

Electrical

Characteristics

and

Operating

Conditions for range.

38, 39, 42, 43, 83, 84

----

No Connect:

These pins can be left floating or connected to GND to minimize thermal

impedance.

38, 39, 42, 43

DNU

----

Do Not Use: These signals may with be unconnected or wired to GND to

minimize thermal impedance.

83, 84

----

No Function: These pins are internally connected to the die and will have the

capacitance of an input pin. It is allowable to leave these pins unconnected or

driven by signals. Pins 83 and 84 are reserved for address expansion.

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

First Address

(external)

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

X...X00 X...X01 X...X10 X...X11
X...X01 X...X00 X...X11 X...X10
X...X10 X...X11 X...X00 X...X01
X...X11 X...X10 X...X01 X...X00

First Address

(external)

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

X...X00 X...X01 X...X10 X...X11
X...X01 X...X10 X...X11 X...X00
X...X10 X...X11 X...X00 X...X01
X...X11 X...X00 X...X01 X...X10

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

LINEAR BURST ADDRESS TABLE (MODE = LOW)

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS*

FUNCTION

R/W\

BWa\

BWb\

BWc\

BWd\

READ

Write Abort/NOP

Write Byte a (DQa, DQPa)

Write Byte b (DQb, DQPb)

Write Byte c (DQc, DQPc)

Write Byte d (DQd, DQPd)

Write all bytes

NOTE:

Using R/W\ and byte write(s), any one or more bytes may be written.

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

FUNCTIONAL BLOCK DIAGRAM

NOTE:

The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed

information.

SA0, SA1, SA

SA1'

SA0'

MODE

ADV/LD\

CLK

CKE\

ADV/LD\

BWa\

BWb\

DQs

BWc\

BWd\

R/W\

OE\

CE\

CE2

CE2\

128K X 9 X 4

MEMORY

ARRAY

WRITE

DRIVERS

WRITE REGISTRY AND

DATA COHERENCY

CONTROL LOGIC

READ

LOGIC

INPUT

WRITE ADDRESS

ADDRESS

BURST

LOGIC

SA1

SA0

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

TRUTH TABLE

(5-10

)

NOTE:

CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ
or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a
DESELECT cycle is first executed.

DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.

A WRITE ABORT means a WRITE command is given, but no operation is performed.
3.

OE\ may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. OE\ may be used when the bus turn-on and turn-off times do not meet an applications
requirements.

If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.

X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa\, BWb\, BWc\,
BWd\) are HIGH. BWx = L means all byte write signals are LOW.

BWa\ enables WRITES to Byte "a" (DQa pins); BWb\ enables WRITES to Byte "b" (DQb pins); BWc\ enables WRITES to
Byte "c" (DQc pins); BWd\ enables WRITES to Byte "d" (DQd pins).

All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

Wait states are inserted by setting CKE\ HIGH.

This device contains circuitry that will ensure that the outputs will be in the High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.

OPERATION

ADDRESS

USED

CE\

CE2\

CE2

ADV/LD\

R/W\

BWx

OE\

CKE\

CLK

NOTES

DESELECT CYCLE

None

High-Z

DESELECT CYCLE

None

High-Z

DESELECT CYCLE

None

High-Z

CONTINUE DESELECT CYCLE

None

High-Z

READ CYCLE

(Begin Burst)

External

READ CYCLE

(Continue Burst)

1, 11

NOP/DUMMY READ

(Begin Burst)

External

High-Z

DUMMY READ

(Continue Burst)

High-Z

1, 2, 11

WRITE CYCLE

(Begin Burst)

External

WRITE CYCLE

(Continue Burst)

1, 3, 11

NOP/WRITE ABORT

(Begin Burst)

None

High-Z

2, 3

WRITE ABORT

(Continue Burst)

High-Z

1, 2, 3,

IGNORE CLOCK EDGE

(Stall)

Current

---

SNOOZE MODE

None

High-Z

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Supply Relative to V

.................-0.5V to +4.6V

Voltage on V

Q Supply Relative to V

.................-0.5V to V

.................................................................. -0.5V to V

Q +0.5V

Storage Temperature (Plastics) ..........................-55

C to +150

Short Circuit Output Current .............................................100mA
Max. Junction Temperature*.............................................+150

*Stresses greater than those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operation section of this speci-
fication is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
**Junction Temperature depends upon package type, cycle time, load-
ing, ambient temperture and airflow.

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55

C < T

< +125

C; V

DD,

Q = +3.3V +0.165V unless otherwise noted)

NOTE:

All voltages referenced to V

(GND).

Overshoot: V

< +4.6V for t < t

KHKH

/2 for I < 20mA.

Undershoot: V

< -0.7V for t < t

KHKH

/2 for I < 20mA.

Power-up: V

< +3.465V and V

< 3.135V for t < 200ms.

MODE pin has an internal pull-up, and input leakage = + 10

The load used for V

, V

testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curvers

are available upon request.

Q should never exceed V

. V

and V

Q should be externally wired together to the same power supply.

This parameter is sampled.

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

2.0

+ 0.3

1, 2

Input High (Logic 1) Voltage

DQ Pins

2.0

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.8

1, 2

Input Leakage Current

0V < V

< V

-1.0

1.0

Output Leakage Current

Output(s) Disabled,

0V < V

< V

-1.0

1.0

Output High Voltage

= -4.0mA

2.4

---

1, 4

Output Low Voltage

= 8.0mA

---

0.4

1, 4

Supply Voltage

3.135

3.465

Isolated Output Buffer Supply

3.135

1, 5

CAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

NOTES

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

3.5

Clock Capacitance

3.5

= 25

C; f = 1 MHz

= 3.3V

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

DESCRIPTION

CONDITIONS

SYM

-11

-12

UNITS NOTES

Power Supply
Current: Operating

Device selected; All inputs < V

or > V

; Cycle time > t

(MIN)

= MAX; Outputs open

275

250

1, 2

Power Supply
Current: Idle

Device selected; V

= MAX;

CKE\ > V

;

All inputs < V

+ 0.2 or > V

-0.2;

Cycle time > t

(MIN)

DD1

1, 2

CMOS Standby

Device selected; V

= MAX;

All inputs < V

+ 0.2 or > V

-0.2;

All inputs static; CLK frequency = 0

SB2

TTL Standby

Device selected; V

= MAX;

All inputs < V

or > V

;

All inputs static; CLK frequency = 0

SB3

Clock Running

Device selected; V

= MAX;

ADV/LD\ > V

; All inputs < V

+ 0.2

or > V

- 0.2; Cycle time > t

(MIN)

SB4

Snooze Mode

ZZ > V

SB2Z

MAX

OPERATING CONDITIONS AND MAXIMUM LIMITS

(-55

C < T

< +125

C; V

DD,

Q = +3.3V +0.165V unless otherwise noted)

THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYM

TYP

UNITS

NOTES

Thermal Resistance
(Junction to Ambient)

C/W

Thermal Resistance
(Junction to Top of Case)

2.8

C/W

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51

NOTE:

is specified with no output current and increases with faster cycle times. I

Q increases with faster cycle times and

greater output loading.

"Device deselected" means device is in a deselected cycle as defined in the truth table. "Device selected" means device
is active (not in deselected mode).

This parameter is sampled.

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

DESCRIPTION

SYM

MIN

MAX

MIN

MAX

UNITS

NOTES

CLOCK

Clock cycle time

KHKH

Clock frequency

MHz

Clock HIGH time

KHKL

3.0

Clock LOW time

KLKH

3.0

OUTPUT TIMES

Clock to output valid

KHQV

8.5

9.0

Clock to output invalid

KHQX

3.0

Clock to output in Low-Z

KHQX1

3.0

2, 3, 4, 5

Clock to output in High-Z

KHQZ

5.0

2, 3, 4, 5

OE\ to output valid

GLQV

5.0

OE\ to output in Low-Z

GLQX

2, 3, 4, 5

OE\ to output in High-Z

GHQZ

5.0

2, 3, 4, 5

SETUP TIMES

Address

AVKH

2.2

2.5

Clock enable (CKE\)

EVKH

2.2

2.5

Control signals

CVKH

2.2

2.5

Data-in

DVKH

2.2

2.5

HOLD TIMES

Address

KHAX

0.5

Clock enable (CKE\)

KHEX

0.5

Control signals

KHCX

0.5

Data-in

KHDX

0.5

-11

-12

AC ELECTRICAL CHARACTERISTICS

6, 8, 9

(-55

C < T

< +125

C; V

DD,

Q = +3.3V +0.165V)

NOTE:

1 .

Measured as HIGH above V

and LOW below V

2 .

Contact ASI for more information on these parameters.

This parameter is sampled.

4 .

This parameter is measured with the output loading shown in Figure 2.

5 .

Transistion is measured +200mV from steady state voltage.

6 .

OE\ can be considerted a "Don't Care" during WRITEs; however, controlling OE\ can help fine-tune a system for ZBL timing.

7 .

This is a synchrnous device. All addresses must meet the specified setup and hold times for all rising edgges o CLK when they are being
registered into the device. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of
clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADV/LD\ is LOW to remain enabled.

8 .

Test conditions as specified with the output loading shown in Figure 1, unless otherwise noted.

9 .

A WRITE cycle is defined by R/W\ LOW having been registered into the device at ADV/LD\ LOW. A READ cycle is defined by R/W\
HIGH with ADV/LD\ LOW. Both cases must meet setup and hold times.

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

SNOOZE MODE

SNOOZE MODE is a low-current, "power-down" mode

in which the device is deselected and current is reduced to

SB2Z

. The duration of SNOOZE MODE is dictated by the

length of time the ZZ pin is in a HIGH state. After the device
enters SNOOZE MODE, all inputs except ZZ become dis-
abled and all outputs go to High-Z.

The ZZ pin is an asynchronous, active HIGH input that

causes the device to enter SNOOZE MODE. When the ZZ pin

becomes a logic HIGH, I

SB2Z

is guaranteed after the time t

ZZI

is met. Any READ or WRITE operation pending when the
device enters SNOOZE MODE is not guaranteed to complete
sucessfully. Therefore, SNOOZE MODE must not be initiated
until valid pending operations are completed. Similarly, when

exiting SNOOZE MODE during t

RZZ

, only a DESELECT or READ

cycle should be given.

SNOOZE MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION

CONDITIONS

SYM

MIN

MAX

UNITS NOTES

Current during SNOOZE MODE

ZZ > V

SB2Z

ZZ active to input ignored

KHKH

ZZ inactive to input sampled

RZZ

KHKH

ZZ active to snooze current

ZZI

KHKH

ZZ inactive to exit snooze current

RZZI

SNOOZE MODE WAVEFORM

CLK

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

12345

12345678901234567890

12345

12345678901234567890

123456

12345

123456789012345678901

DESELECT

or READ Only

RZZ

ZZI

ISB2Z

High-Z

RZZI

12345

Don't Care

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

READ/WRITE TIMING

READ/WRITE TIMING PARAMETERS

MIN

MAX

MIN

MAX

KHKH

KHKL

3.0

KLKH

3.0

KHQV

8.5

9.0

KHQX

3.0

KHQX1

3.0

KHQZ

5.0

GLQV

5.0

GLQX

SYMBOL

-12

-11

MIN

MAX

MIN

MAX

GHQZ

5.0

AVKH

2.2

2.5

EVKH

2.2

2.5

CVKH

2.2

2.5

DVKH

2.2

2.5

KHAX

0.5

KHEX

0.5

KHCX

0.5

GLDX

0.5

SYMBOL

-12

-11

NOTE:

1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0=linear, 1=interleaved). BURST operations are optional.
3. CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.

1234

123

1234

123

1234

123456789

12345678

1234

123

1234

1234567890

1234

1234567890

1234

1234567890

1234

123456789012345678901

12345678

123456789

1234

123

1234567

123

1234567

123

1234567

1234

D(A1)

123

D(A2)

123

D(A2+1)

123

Q(A3)

Q(A4)

Q(A4+1)

123

D(A5)

Q(A6)

123

D(A7)

WRITE

D(A1)

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4 +1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

123

Don't Care

1234

Undefined

CLK

CLE\

CE\

ADV/LD\

R/W\

BWx\

ADDRESS

OE\

COMMAND

2 3 4 5 6 7 8 9 10

KHKH

KHKL

KLKH

EVKH

KHEX

CVKH

KHCX

AVKH

KHAX

DVKH

KHDX

KHQX1

KHQV

KHQX

GHQZ

GLQX

GLQV

KHQX

KHQZ

SRAM

AS5SS128K36

Austin Semiconductor, Inc.

AS5SS128K36

Rev. 2.0 12/00

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

NOP, STALL AND DESELECT CYCLES

123

1234

1234567890123456

1234

1234567890123456789012

12345678901234567890123

123

12345678901234

123

12345678901234

123

D(A1)

1234

Q(A2)

123

Q(A3)

123

Q(A5)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT CONTINUE

DESELECT

123

Don't Care

1234

Undefined

CLK

CE\

ADV/LD\

R/W\

BWx\

ADDRESS

COMMAND

2 3 4 5 6 7 8 9 10

KHQX

KHQZ

1234

123

1234

123

1234

CKE\

1234

12345678

123

1234

12345678

123456789

123

1234

123456789

12345678

123456789

1234567890

D(A4)

NOP, STALL AND DESELECT TIMING PARAMETERS

MIN

MAX

MIN

MAX

KHQX

3.0

KHQZ

5.0

SYMBOL

-12

-11

NOTE:

The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE\ being used to create a "pause". A WRITE is not performed
during this cycle.

For this waveform, ZZ and OE\ are tied LOW.

CE\ represents three signals. When CE\ = 0, it represents CE\ = 0, CE2\ = 0, CE2 = 1.

Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data
may be from the input data register.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS5SS128K36DQ-11/IT

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AS5SS128K36DQ-11/IT