UVEPROM
UVEPROM
UVEPROM
UVEPROM
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
Rev. 2.0 3/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Organized 131,072 x 8
Single +5V 10% power supply
Operationally compatible with existing megabit EPROMs
Industry standard 32-pin ceramic dual-in-line package
All inputs/outputs fully TTL compatible
8-bit output for use in microprocessor-based systems
Very high-speed SNAP! Pulse Programming
Power-saving CMOS technology
3-state output buffers
400mV minimum DC noise immunity with standard
TTL loads
Latchup immunity of 250 mA on all input and output pins
No pullup resistors required
Low power dissipation (Vcc = 5.5V)
!
Active - 165 mW Worst Case
!
Standby - 0.55 mW Worst Case (CMOS-input levels)
OPTIONS
MARKING
Timing
120ns access
-12
150ns access
-15
200ns access
-20
Package(s)
Ceramic DIP (600mils) J or ECA No. 114
Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
M
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-89614
MIL-STD-883
32-Pin DIP (J)
(600 MIL)
1 MEG UVEPROM
UV Erasable Programmable
Read-Only Memory
For more products and information
please visit our web site at
www.austinsemiconductor.com
GENERAL DESCRIPTION
The SMJ27C010A series are 131072 by 8-bit (1048576-
bit), ultaviolet (UV) light erasable, electrically programmable
read-only memories (EPROMs).
These devices are fabricated using power-saving CMOS
technology for high speed and simple interface with MOS and
bipolar circuits. All inputs (including program data inputs)
can be driven by Series 54 TTL circuits without the use of
external pullup resistors. Each output can drive one Series 54
TTL circuit without external resistors.
The SMJ27C010A EPROM is offered in a ceramic
dual-in-line package (J suffix) designed for insertion in
mounting-hole rows on 15.2mm (600mil) centers.
These EPROMs operate from a single 5V supply (in the
read mode), and therefore, are ideal for use in
microprocessor-based systems. One other 13V supply is
needed for programming. All programming signals are TTL
level. These devices are programmable using the SNAP! Pulse
programming algorithm. The SNAP! Pulse programming
algorithm uses a V
PP
of 13V and a V
CC
of 6.5V for a nominal
programming time of thirteen seconds. For programming
outside the system, existing EPROM programmers can be
used. Locations can be programmed singly, in blocks, or at
random.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
Vcc
PGM\
NC
A14
A13
A8
A9
A11
G\
A10
E\
DQ7
DQ6
DQ5
DQ4
DQ3
Pin Name
Function
A0 - A18
Address Inputs
DA0-DQ7 Inputs (programming)/Outputs
E\
Chip Enable
G\
Output Enable
GND
Ground
PGM\
Program
V
CC
5V Supply
V
PP
13V Power Supply*
*Only in program mode.
UVEPROM
UVEPROM
UVEPROM
UVEPROM
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
Rev. 2.0 3/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM*
OPERATION
The seven modes of operation are listed in Table 1. The read mode requires a single 5V supply. All inputs are TTL level
except for V
PP
during programming (13V for SNAP! Pulse), and 12V on A9 for signature mode.
TABLE 1. OPERATION MODES
* X can be V
IL
or V
IH
.
**V
H
= 12V 0.5V
A0
A1
A2
A3
A4
A5
DQ0
A6
DQ1
A7
DQ2
A8
DQ3
A9
DQ4
A10
DQ5
A11
DQ6
A12
DQ7
A13
A14
A15
A16
E\
G\
&
12
[PWR DWN]
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
EN
A
A
A
A
A
A
A
A
13
14
15
17
18
19
20
21
EPROM 131,072 x 8
0
16
A
0
131,071
READ
OUTPUT
DISABLE
STANDBY PROGRAMMING
VERIFY
PROGRAM
INHIBIT
E\
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
G\
V
IL
V
IH
X
V
IH
V
IL
X
PGM\
X
X
X
V
IL
V
IH
X
V
PP
V
CC
V
CC
V
CC
V
PP
V
PP
V
PP
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
A9
X
X
X
X
X
X
V
H
**
V
H
**
A0
X
X
X
X
X
X
V
IL
V
IH
MFG
DEVICE
97
D6
V
CC
DQ0-DQ7
Data Out
High-Z
High-Z
Data In
Data Out
High-Z
CODE
V
IL
V
IL
X
V
CC
FUNCTION
SIGNATURE MODE
MODE*
* This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. J package illustrated.
UVEPROM
UVEPROM
UVEPROM
UVEPROM
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
Rev. 2.0 3/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
READ/OUTPUT DISABLE
When the outputs of two or more SMJ27C010As are
connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no
interference from competing outputs of the other devices. To
read the output of a single device, a low level signal is applied
to the E\ and G\ pins. All other devices in the circuit should
have their outputs disabled by applying a high-level signal to
one of these pins.
LATCHUP IMMUNITY
Latchup immunity on the SMJ27C010A is a minimum of
250mA on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the devices are interfaced to
industry-standard TTL or MOS logic devices. The input/
output layout approach controls latchup without
compromising performance or packing density.
POWER DOWN
Active I
CC
supply current can be reduced from 30mA to 500A
by applying a high TTL input on E\ and to 100A by applying a
high CMOS input on E\. In this mode all outputs are in the
high-impedance state.
ERASURE
Before programming, the SMJ27C010A EPROM is erased
by exposing the chip through the transparent lid to a high-
intensity ultraviolet light (wavelength 2537 ). The
recommended minimum exposure dose (UV intensity x
exposure time) is 15-W
.
s/cm
2
. A typical 12-mW/cm
2
,
filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5cm above the chip during erasure.
After erasure, all bits are in the high state. It should be noted
that normal ambient light contains the correct wavelength for
erasure; therefore, when using the SMJ27C010A, the window
should be covered with an opaque label. After erasure (all
bits in logic high state), logic lows are programmed into the
desired locations. A programmed low can be erased only by
ultraviolet light.
SNAP! PULSE PROGRAMMING
The SMJ27C010A is programmed by using the SNAP! Pulse
programming algorithm as illustrated by the flow chart
(Figure 1). This algorithm programs in a nominal time of
thirteen seconds. Actual programming time varies as a
function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse
of 100 microseconds (s) followed by a byte verification to
determine when the addressed byte has been successfully
programmed. Up to ten 100s pulses per byte are provided
before a failure is recognized.
The programming mode is achieved when V
PP
= 13V,
V
CC
= 6.5V, E\ = V
IL
, and G\ = V
IH
. Data is presented in
parallel (eight bits) on pins DQ0 through DQ7. Once addresses
and data are stable, PGM\ is pulsed low.
More than one device can be programmed when the devices
are connected in parallel. Locations can be programmed in
any order. When the SNAP! Pulse programming routine is
complete, all bits are verified with V
CC
= V
PP
= 5V 10%.
PROGRAM INHIBIT
Programming can be inhibited by maintaining high level
inputs on the E\ or the PGM\ pins.
PROGRAM VERIFY
Programmed bits can be verified with V
PP
= 13V when
G\ = V
IL
, and E\ = V
IL
, and PGM\ = V
IH
.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and type. This mode is activated
when A9 (pin 26) is forced to 12V. Two identifier bytes are
accessed by toggling A0. All other addresses must be held
low. The signature code for these devices is 97D6. A0 low
selects the manufacturer's code 97 (Hex), and A0 high
selects the device code D6 (Hex), as shown in Table 2.
TABLE 2. SIGNATURE MODES
* E\ = G\ = V
IL
, A1 - A8 = V
IL
, A9 = V
H
, A10 - A16 = V
IL
, V
PP
= V
CC
.
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0 HEX
MANUFACTURER CODE
V
IL
1
0
0
1
0
1
1
1
97
DEVICE CODE
V
IH
1
1
0
1
0
1
1
0
D6
IDENTIFIER*
PINS
UVEPROM
UVEPROM
UVEPROM
UVEPROM
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
Rev. 2.0 3/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART
START
Address = First Location
Increment Address
X = 0
Last
Address?
V
CC
= V
PP
= 5V 0.5V
Compare
All Bytes
to Original
Data
Device Passed
Increment
Address
Address = First Location
V
CC
= 6.5V 0.25V, V
PP
= 13V 0.25V
Program One Pulse = t
W
= 100s
Last
Address?
X = X+1
X = 10?
Program One Pulse = t
W
= 100s
No
Fail
No
Yes
Verify
One
Byte
No
Pass
Device Failed
Yes
Yes
Pass
Fail
Program
Mode
Interactive
Mode
Final
Verification
UVEPROM
UVEPROM
UVEPROM
UVEPROM
UVEPROM
SMJ27C010A
AS27C010A
Austin Semiconductor, Inc.
SMJ27C010A
AS27C010A
Rev. 2.0 3/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
** All voltage values are with respect to GND.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range, V
CC
**...........................-0.6V to +7.0V
Supply Voltage Range, V
pp
**.........................-0.6V to +14.0V
Input Voltage Range, All inputs except A9
**
..-0.6V to V
CC
+1
A9.....-0.6V to +13.5V
Output Voltage Range,
with respect to V
SS
**..................................-0.6V to V
CC
+1
Operating Free-air Temperature Range, T
A
....-55C to 125C
Storage Temperature Range, T
stg
.....................-65C to 150C
RECOMMENDED OPERATING CONDITIONS
NOTES:
1. V
CC
must be applied before or at the same time as V
PP
and removed after or at the same time as V
PP
. The deivce must not be inserted into or removed from
the board when V
PP
or V
CC
is applied.
2. During programming, V
PP
must be maintained at 13V 0.25V.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
NOTES:
1. Minimum cycle time = maximum access time.
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
6.25
6.5
6.75
V
V
CC
-0.6
V
CC
V
CC
+0.6
V
12.75
13
13.25
V
TTL
2
V
CC
+0.5
V
CMOS
V
CC
-0.2
V
CC
+0.5
V
TTL
-0.5
0.8
V
CMOS
-0.5
GND+0.2
V
T
A
-55
125
C
V
IL
Low-level DC input voltage
Operating free-air temperature
Read Mode
2
SNAP! Pulse programming algorithm
V
PP
High-level DC input voltage
V
IH
Supply Voltage
V
CC
Read Mode
1
SNAP! Pulse programming algorithm
Supply Voltage
TEST CONDITIONS
MIN
MAX
UNIT
I
OH
= -20A
V
CC
-0.2
I
OH
= -2.5mA
3.5
I
OL
= 2.1mA
0.4
I
OL
= 20A
0.1
I
I
V
I
= 0V to 5.5V
1
A
I
O
V
O
= 0V to V
CC
1
A
I
PP1
V
PP
= V
CC
= 5.5V
10
A
I
PP2
V
PP
= 13V
50
mA
TTL-Input Level
V
CC
= 5.5V, E\=V
IH
500
CMOS-Input Level
V
CC
= 5.5V, E\=V
CC
0.2V
100
I
CC2
E\=V
IL
, V
CC
=5.5V
t
cycle
= minimum cycle time,
outputs open
1
30
mA
A
High-level DC output voltage
Low-level DC output voltage
V
V
V
CC
supply current (active) (output open)
PARAMETER
I
CC1
V
CC
supply current (standby)
Input current (leakage)
V
PP
supply current
Output current (leakage)
V
PP
supply current (during program pulse)
V
OL
V
OH
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