AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690
AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690
February 24, 2003
3
AL4CX3650/AL4CX3660/AL4CX3670/AL4C
X3680/AL4CX3690 (2K x36, 4K x36, 8K x36,
16K x36, 32K x36) Synchronous FIFO
Contents:
1.0 Description _________________________________________________________________ 5
2.0 Features____________________________________________________________________ 5
3.0 Applications_________________________________________________________________ 6
4.0 Chip Information ____________________________________________________________ 7
4.1 Marking Information ______________________________________________________________ 7
4.2 Ordering Information______________________________________________________________ 7
5.0 Pin Diagram ________________________________________________________________ 8
6.0 Block Diagram ______________________________________________________________ 8
7.0 Pin Definition and Description _________________________________________________ 9
8.0 Function Description ________________________________________________________ 13
8.1 Timing Modes: Standard vs. First Word Fall Through (FWFT) Mode _____________________ 14
8.2 Standard Mode __________________________________________________________________ 15
8.3 First Word Fall Through Mode (FWFT) _____________________________________________ 16
8.4 Programmable Flag Offsets ________________________________________________________ 17
9.0 Memory Operations: _________________________________________________________ 24
9.1 Inputs and Outputs: ______________________________________________________________ 24
9.2 Flags: __________________________________________________________________________ 24
9.3 Controls: _______________________________________________________________________ 26
10.0 Electrical Characteristics ____________________________________________________ 32
10.1 Absolute Maximum Ratings _______________________________________________________ 32
10.2 Recommended Operating Conditions _______________________________________________ 32
10.3 DC Characteristics ______________________________________________________________ 33
10.4 AC Electrical Characteristics______________________________________________________ 33
10.5 Timing Diagrams________________________________________________________________ 35
11.0 Mechanical Drawing _______________________________________________________ 50
11.1 14x20mm 128-Pin TQFP Package __________________________________________________ 50
AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690
AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690
February 24, 2003
5
1.0 Description
The AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690 series products are high-
performance, low-power 36bit read/write synchronous FIFO (First-In-First-Out) memory chips.
They are specially designed to buffer high speed streaming data for a wide range of multimedia and
communication applications, such as optical disk controllers, Local Area Networks (LANs), SONET
(Synchronous Optical Network).
The AL4CX3650/AL4CX3660/AL4CX3670/AL4CX3680/AL4CX3690 FIFO (First In First Out)
memory provides completely independent 36bit bus width input and output port operation with
flexible x36/ x18/ x9 Bus-Matching data flow control at a maximum speed of 166 MHz. The
products are available in densities from 64Kbit to 1Mbit with word depths from 2K to 32K.
Additional features of the AL4CX36x0 series include: fixed and programmable flags; low first word
latency; partial reset; Endian select; expandable depth/width and optional first-word-fall-through.
The embedded memory array with built-in address decoder, pointer manager and state-of-the-art
circuits provide an easy-to-use interface to serial read/write memory and offer a flexible way to
manage memory in the system design.
The input port of the FIFO is controlled by a free running clock (WCLK), and an input enable
(/WEN). The output port is controlled by another clock (RCLK) and an output enable (/REN). Data
is read into or output from FIFO synchronous on every individual WRCK or RCLK clock cycle
when /WEN or /REN is asserted respectively.
These FIFOs support selectable bus width up to 36bit for both input and output ports and can be
configured as x36 to x36, x36 to x18, x36 to x9, x18 to x36 and x9 to x36 multiple input and output
port bus width. This allows for easy conversion of the bus width between the input flow and output
flow.
There are two fixed flags, Empty Flag/Output Ready and Full Flag/Input Ready, and two
programmable flags, Almost-Empty and Almost-Full. The flags enable further manipulation of the
synchronous control.
Multiple AL4CX36x0s can be cascaded to expand the storage depth or can be used in parallel to
expand bus width. The FIFOs are 3.3-volt devices with 5-volt input tolerance. And are available in
the 128-pin thin quad flat Pack (TQFP Package).
2.0 Features
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2,048 x36 bit organization (AL4CX3650)
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4,096 x36 bit organization (AL4CX3660)
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8,192 x36 bit organization (AL4CX3670)
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16,384 x36 bit organization (AL4CX3680)
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32,768 x36 bit organization (AL4CX3690)
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166 MHz Operation
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6 ns read/write cycle time
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