2DAC-C16R Series - Integrated Passive & Active Device using CSP
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
SOLDER
BUMPS
SILICON
DIE
Electrical Characteristics
Symbol
Minimum
Nominal
Maximum
Unit
(T
A
= 25 C unless otherwise noted)
Zener Diode
Breakdown Voltage @ 1 mA
V
BR
6
7.2
8
V
Leakage Current @ 3 V
I
R
1 uA
Diode Capacitance @ 1 V & 1 MHz
C
T
8.5
10.5
12.5 pF
ESD Performance (Note 1 & 2)
Withstand
Contact Discharge
8
kV
Air Discharge
15
kV
Let Through
Contact Discharge
150 V
Air Discharge
150 V
Thermal Characteristics
(T
A
= 25 C unless otherwise noted)
Operating Temperature
T
J
-40 25 +85 C
Storage Temperature
T
stg
-60 25 +125 C
Total Power Dissipation @ 70 C
P
D
100 mW
General Information
Features
Lead free versions available
RoHS compliant (lead free version)*
New Product Development
Integrated Passive Device
ESD Protection to IEC61000-4-2 Spec.
Electrical & Thermal Characteristics
This application specific integrated passive component is
designed to provide all of the necessary ESD protection
on the data port of a portable electronic device. The ESD
protection provided by the component enables the data
port to withstand 8 KV Contact / 15 KV Air Discharge
when tested according to the method specified in IEC
61000-4-2. The component incorporates 12 identical ports
and is supplied in a 16 pin CSP package which is intended
to be mounted directly onto an FR4 printed circuit board.
This package is designed to meet typical thermal cycle
and bend test specifications without the use of an
underfill material.
Note:
1. The IEC 61000-4-2 test method will be adapted for component level testing. The device will provide the specified ESD protection
performance on the "EXT1 12" pins only.
2. "Let Through" is a measure of the component of an incident ESD transient that the protection device allows through to the down
stream circuitry.
Figure 1 CSP Format
*RoHS COMPLIANT
VERSIONS
AVAILABLE
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
DIMENSIONS =
MICRONS
(MILS)
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Mechanical Characteristics
2DAC-C16R Series - Integrated Passive & Active Device using CSP
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
858 40
(33.78 1.57)
225 20
(8.86 0.79)
1997 45
(78.62 1.78)
2177 45
(85.71 1.78)
500
(19.69)
300
(11.81)
500
(19.69)
BUMP A1/PIN 1
INDICATOR
BOURNS
LOGO
45 45
(1.78 1.78)
45 45
(1.78 1.78)
248.5 45
(9.78 1.78)
248.5 45
(9.78 1.78)
428.5 45
(16.87 1.78)
DIA.
This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5 mm. The dimensions for the CSP packaged device are shown in Fig. 2 below.
Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP
packaging.
"Package level" testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2DAC-C16R and is thus deemed a
worse case for Thermal Cycle testing.
"Silicon level" reliability performance will be assured by similarity to other Integrated Passive and Active Devices using CSP product
from Bourns.
Fig. 2 Device Mechanical Drawing
Reliability
This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical
parameter of primary interest is the ESD performance.
Key Design Parameters
Zener Diode
V
BR
: 6 V Min, 8 V Max @ I
BR
= 1 mA
I
R
: 1 uA Max @ V
R
= 3 V
C
T
: 8.5 pF Min, 10.5 pF Typ, 12.5 pF Max @ V
R
= 1 V & F = 1 MHz
Individual Channel Schematic
6.5 V
EXT1-12
GROUND
Fig. 3 Channel Schematic
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2DAC-C16R Series - Integrated Passive & Active Device using CSP
Block Diagram
GROUND
GROUND
GROUND
GROUND
EXT1
EXT12
6.5 V
6.5 V
EXT2
EXT11
6.5 V
6.5 V
EXT3
EXT10
6.5 V
6.5 V
EXT4
EXT9
6.5 V
6.5 V
EXT5
EXT8
6.5 V
6.5 V
EXT6
EXT7
6.5 V
6.5 V
PIN A1
LOCATION
A
B
C
D
1 2 3 4
DAC
Lotcode
Figure 4 contains a block diagram of the CSP device. This diagram includes the pin
names and basic electrical connections associated with each channel.
The device will be laser marked on the
backside according to the following
Fig. 5 scheme below. Position A1, on the
Bump Grid is located at the top left of
the die when the die is orientated so that
the mark is read in the normal fashion.
Marking
Please consult Bourns' Thin Film on
Silicon using CSP Users Guide
Application Note for notes on PCB
design and SMT processing.
PCB Design and SMT Processing
Fig. 4 Device Block Diagram
Fig. 5 Backside Laser Mark
How to Order
2 DAC - C16R __
__
Thinfilm
Model
Chipscale
No. of Solder Bumps
Packaging Option
R = Tape and Reel
Packaged 3000 pcs. / 7 " reel
Terminations
LF = Sn/Ag/Cu (lead free)
Blank = Sn/Pb
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2DAC-C16R 02/05
2DAC-C16R Series - Integrated Passive & Active Device using CSP
The Pin-Out for the device is shown in Fig. 6. Note also that the device is shown with bumps facing up.
Device Pin Out
The product will be dispensed in an 8mm x 4mm Tape and Reel format - see Fig. 7 diagram below. The Tape and Reel package will
conform to customer specification.
Packaging
EXT11
EXT10
EXT4
EXT12
EXT1
EXT8
EXT2
EXT3
EXT4
EXT5
EXT7
EXT6
GROUND
X 4
1
2
3
4
D
C
B
A
2.0 0.05
(.08 .002)
0.3 0.05
(.01 .002)
2.12 0.05
(.08 .002)
2.30 0.05
(.09 .002)
1.75 0.1
(.07 .004)
3.5 0.05
(.14 .002)
8.0 0.3
(.31 .01)
0.90 0.05
(.04 .002)
ORIENTATION
OF COMPONENT
IN POCKET
BACKSIDE FACING UP
0.3
(0.01)
4.0 0.1
(.16 .004)
4.0 0.1
(.16 .004)
0.25
(0.001)
TYP.
R
1.5 0.1/-0
(.06 .004/-0)
DIA.
MAX.
R
Fig. 6 (a) - Device Pin Out "Bumps Up" View
Fig. 6 (b) - Pin Listings
Fig. 7 - Tape and Reel Drawing
Pin Name
Pin Name
A1 EXT2
C1 EXT12
A2 EXT3 C2 GND
A3 EXT4
C3 GND
A4 EXT5
C4 EXT7
B1 EXT1
D1
EXT11
B2 GND
D2
EXT10
B3 GND
D3
EXT9
B4 EXT6 D4
EXT8
DIMENSIONS =
MILLIMETERS
(INCHES)
Asia-Pacific: TEL +886- (0)2 25624117 FAX +886- (0)2 25624116
Europe: TEL +353 214 515 225 FAX +353 214 515 292
The Americas: TEL +1-909 781-5492 FAX +1-909 781-5700
www.bourns.com
Reliable Electronic Solutions
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