Ultra Low Power/High Speed CMOS SRAM
1M X 8 bit
BH62UV8000
Green package materials are compliant to RoHS
R0201-BH62UV8000
Revision
1.1
Dec.
2005
1
n
FEATURES
Y
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Y
Ultra low power consumption :
V
CC
= 3.6V
Operation current : 12mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 2.5uA (Typ.) at 25
O
C
V
CC
= 1.2V
Data retention current : 1.2uA (Typ.) at 25
O
C
Y
High speed access time :
-55
55ns (Max.) at V
CC
=1.65~3.6V
Y
Automatic power down when chip is deselected
Y
Easy expansion with CE1, CE2 and OE options
Y
Three state outputs and TTL compatible
Y
Fully static operation, no clock, no refresh
Y
Data retention supply voltage as low as 1.0V
n
DESCRIPTION
The BH62UV8000 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.6V/25
O
C and maximum access time of 55ns at
1.65V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8000 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH62UV8000 is available in DICE form, JEDEC standard 48-pin
TSOP-I and 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
V
CC
=3.6V
V
CC
=1.8V
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
=3.6V V
CC
=1.8V
1MHz
10MHz
f
Max.
1MHz
10MHz
f
Max.
PKG TYPE
BH62UV8000DI
DICE
BH62UV8000AI
Industrial
-25
O
C to +85
O
C
15uA
12uA
2mA
6mA
12mA
1.5mA
5mA
8mA
BGA-48-0608
n
PIN CONFIGURATIONS
n
BLOCK DIAGRAM
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 8192
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A15
A13 A16 A2 A1
Data
Input
Buffer
Control
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
8
8
8
8
10
1024
8192
1024
10
A17
A19
Data
Output
Buffer
A14
CE1
CE2
WE
OE
V
CC
GND
A0
A18
G
H
F
E
D
C
B
A
1
2
3
4
5
6
A9
A11
A10
A19
A12
A14
A13
A15
WE
NC
NC
NC
DQ7
A17
A16
A7
VSS
VCC
DQ2
DQ1
DQ6
DQ5
VCC
A5
OE
A3
A0
A6
A4
A1
A2
CE2
NC
NC
NC
CE1
DQ4
NC
48-ball BGA top view
NC
NC
DQ0
VSS
VCC
DQ3
NC
A18
NC
A8
BH62UV8000
R0201-BH62UV8000
Revision
1.1
Dec.
2005
2
n
PIN DESCRIPTIONS
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 8 bit in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
8 bi-directional ports are used to read data from or write data into the RAM.
V
CC
Power Supply
V
SS
Ground
n
TRUTH TABLE
MODE
CE1
CE2
WE
OE
I/O OPERATION
V
CC
CURRENT
H
X
X
X
Chip De-selected
(Power Down)
X
L
X
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
H
High Z
I
CC
Read
L
H
H
L
D
OUT
I
CC
Write
L
H
L
X
D
IN
I
CC
NOTES: H means V
IH
; L means V
IL
; X means don
'
t care (Must be V
IH
or V
IL
state)
n
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5
(2)
to 4.6V
V
T
BIAS
Temperature Under
Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
2.0V in case of AC pulse width less than 30 ns
n
OPERATING RANGE
RANG
AMBIENT
TEMPERATURE
V
CC
Industrial
-25
O
C to + 85
O
C
1.65V ~ 3.6V
n
CAPACITANCE
(1)
(T
A
= 25
O
C, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
C
IN
Input
Capacitance
V
IN
= 0V
6
pF
C
IO
Input/Output
Capacitance
V
I/O
= 0V
8
pF
1. This parameter is guaranteed and not 100% tested.
BH62UV8000
R0201-BH62UV8000
Revision
1.1
Dec.
2005
3
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -25
O
C to +85
O
C)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
V
CC
Power Supply
1.65
--
3.6
V
V
CC
=1.8V
0.4
V
IL
Input Low Voltage
V
CC
=3.6V
-0.3
(2)
--
0.6
V
V
CC
=1.8V
1.4
V
IH
Input High Voltage
V
CC
=3.6V
2.2
--
V
CC
+0.3
(3)
V
I
IL
Input Leakage Current
V
IN
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
--
--
1
uA
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
--
--
1
uA
V
CC
= Max, I
OL
= 0.1mA
V
CC
=1.8V
0.2
V
OL
Output Low Voltage
V
CC
= Max, I
OL
= 2.0mA
V
CC
=3.6V
--
--
0.4
V
V
CC
= Min, I
OH
= -0.1mA
V
CC
=1.8V
V
CC
-0.2
V
OH
Output High Voltage
V
CC
= Min, I
OH
= -1.0mA
V
CC
=3.6V
2.4
--
--
V
V
CC
=1.8V
6
8
I
CC
Operating Power Supply
Current
CE1 = V
IL
, CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX
(4)
V
CC
=3.6V
--
8
12
mA
V
CC
=1.8V
1.0
1.5
I
CC1
Operating Power Supply
Current
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
V
CC
=3.6V
--
1.5
2.0
mA
V
CC
=1.8V
0.5
I
CCSB
Standby Current
TTL
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
V
CC
=3.6V
--
--
1.0
mA
V
CC
=1.8V
2.0
12
I
CCSB1
Standby Current
CMOS
CE1
V
CC
-0.2V or CE2
0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
V
CC
=3.6V
--
2.5
15
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
n
DATA RETENTION CHARACTERISTICS (T
A
= -25
O
C to +85
O
C)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
V
DR
V
CC
for Data Retention
CE1
V
CC
-0.2V or CE2
0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
1.0
--
--
V
I
CCDR
(3)
Data Retention Current
CE1
V
CC
-0.2V or CE2
0.2V,
V
IN
V
CC
-0.2V or V
IN
0.2V
V
CC
=1.2V
--
1.2
7.0
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
t
RC
(2)
--
--
ns
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
t
CDR
V
CC
t
R
V
IH
V
IH
CE1
V
CC
- 0.2V
V
DR
1.0V
CE1
V
CC
BH62UV8000
R0201-BH62UV8000
Revision
1.1
Dec.
2005
4
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
V
CC
/ 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
OHZ
, t
WHZ
, t
OW
C
L
= 5pF+1TTL
Output Load
Others
C
L
= 30pF+1TTL
1. Including jig and scope capacitance.
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM
"
H
"
TO
"
L
"
WILL BE CHANGE
FROM
"
H
"
TO
"
L
"
MAY CHANGE
FROM
"
L
"
TO
"
H
"
WILL BE CHANGE
FROM
"
L
"
TO
"
H
"
DON
'
T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
"
OFF
"
STATE
n
AC ELECTRICAL CHARACTERISTICS (T
A
= -25
O
C to +85
O
C)
READ CYCLE
CYCLE TIME : 55ns
JEDEC
PARAMETER
NAME
PARANETER
NAME
DESCRIPTION
MIN.
TYP.
MAX.
UNITS
t
AVAX
t
RC
Read Cycle Time
55
--
--
ns
t
AVQX
t
AA
Address Access Time
--
--
55
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
55
ns
t
E2LQV
t
ACS2
Chip Select Access Time
(CE2)
--
--
55
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
ns
t
E2LQX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output Low Z
5
--
--
ns
t
E1HQZ
t
CHZ1
Chip Select to Output High Z
(CE1)
--
--
25
ns
t
E2HQZ
t
CHZ2
Chip Select to Output High Z
(CE2)
--
--
25
ns
t
GHQZ
t
OHZ
Output Enable to Output High Z
--
--
25
ns
t
AVQX
t
OH
Data Hold from Address Change
10
--
--
ns
C
L
(1)
1 TTL
Output
ALL INPUT PULSES
90%
V
CC
GND
Rise Time:
1V/ns
Fall Time:
1V/ns
90%
10%
10%
CE2
Data Retention Mode
V
CC
t
CDR
V
CC
t
R
V
IL
V
IL
V
CC
V
DR
1.0V
CE2
0.2V
BH62UV8000
R0201-BH62UV8000
Revision
1.1
Dec.
2005
5
n
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1
(1,2,4)
READ CYCLE 2
(1,3,4)
READ CYCLE 3
(1, 4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH
.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured
500mV from steady state with C
L
= 5pF.
The parameter is guaranteed but not 100% tested.
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
(5)
D
OUT
CE2
CE1
t
ACS2
t
ACS1
t
CHZ1
, t
CHZ2
(5)
t
OH
t
RC
t
OE
t
CLZ2
(5)
t
CHZ2
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ1
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
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