Revision 2.3
April. 2002
1
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
1
2
3
4
8
10
11
12
14
16
18
20
22
43
41
39
37
35
34
33
31
29
27
25
23
BS616LV4010EC
BS616LV4010EI
5
6
7
9
13
15
17
19
21
44
42
40
38
36
32
30
28
26
24
R0201-BS616LV4010
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV4010DC
DICE
BS616LV4010EC
BS616LV4010AC
TSOP2-44
BGA-48-0608
BS616LV4010BC
+0
O
C to +70
O
C
2.7V ~ 3.6V
70 / 100
8uA
20mA
BGA-48-0810
BS616LV4010DI
DICE
BS616LV4010EI
BS616LV4010AI
TSOP2-44
BGA-48-0608
BS616LV4010BI
-40
O
C to +85
O
C
2.7V ~ 3.6V
70 / 100
12uA
25mA
BGA-48-0810
Very Low Power/Voltage CMOS SRAM
256K X 16 bit
Very low operation voltage : 2.7 ~ 3.6V
Very low power consumption :
Vcc = 3.0V
C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
-10
100ns (Max.) at Vcc = 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV4010 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV4010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4010 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-pin BGA package.
DESCRIPTION
FEATURES
Row
Decoder
Memory Array
2048 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A9 A8 A7
Data
Input
Buffer
Control
Gnd
Vcc
OE
DQ0
A15
A1
16
16
16
16
WE
CE
DQ15
A0
A13
A14
A2
14
128
2048
BLOCK DIAGRAM
2048
22
A17
A16
A10
A12
A6
A11
A3
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
BS616LV4010
A4
BSI
Revision 2.3
April. 2002
2
R0201-BS616LV4010
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.
CE Chip Enable Input
CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
BS616LV4010
MODE
CE
WE
OE
LB
UB
DQ0~DQ7
DQ8~DQ15
Vcc CURRENT
Not selected
(Power Down)
H
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
X
X
High Z
High Z
I
CC
L
L
Dout
Dout
I
CC
H
L
High Z
Dout
I
CC
Read
L
H
L
L
H
Dout
High Z
I
CC
L
L
Din
Din
I
CC
H
L
X
Din
I
CC
Write
L
L
X
L
H
Din
X
I
CC
Revision 2.3
April. 2002
3
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1 )
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=3.0V
-0.5
--
0.8
V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=3.0V
2.0
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
Vcc=3.0V
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE = V
V
I/O
= 0V to Vcc
IH
, or OE = V
IH
,
--
--
1
uA
V
OL
Output Low Voltage
= 2mA
Vcc = Max, I
OL
Vcc=3.0V
--
--
0.4
V
V
OH
Output High Voltage
= -1mA
Vcc = Min, I
OH
Vcc=3.0V
2.4
--
--
V
I
CC
Operating Power Supply
Current
CE = V
IL
, I
DQ
= 0mA, F = Fmax
(3)
Vcc=3.0V
--
--
20
mA
I
CCSB
Standby Current-TTL
IH
, I
DQ
= 0mA
CE = V
Vcc=3.0V
--
--
1
mA
I
CCSB1
Standby Current-CMOS
CE
V
Vcc-0.2V,
IN
Vcc - 0.2V or V
IN
0.2V
Vcc=3.0V
--
0.5
8
uA
R0201-BS616LV4010
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE
Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE
Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.3
1
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
-
n
-
s
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.7V ~ 3.6V
Industrial
-40
O
C to +85
O
C
2.7V ~ 3.6V
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
BSI
BS616LV4010
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
Revision 2.3
April. 2002
4
R0201-BS616LV4010
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV4010-70
MIN. TYP. MAX.
BS616LV4010-10
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
100
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
--
--
100
ns
t
ELQV
t
ACS
Chip Select Access Time
(CE)
--
--
70
--
--
100
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
--
35
--
--
50
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
35
--
--
50
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE)
10
--
--
15
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,UB)
10
--
--
15
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
15
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE)
0
--
35
0
--
40
ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB,UB)
0
--
35
0
--
40
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
30
0
--
35
ns
t
AXOX
t
OH
Output Disable to Address Change
10
--
--
15
--
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C , Vcc = 3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
CHANGE :
E
STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
100PF
FIGURE 1A
1404
BSI
BS616LV4010
(1)
1. t
BA
is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; t
BA
is 70ns/100ns (@speed=70ns/100ns) without address toggle.
NOTE :
Revision 2.3
April. 2002
5
R0201-BS616LV4010
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
BSI
BS616LV4010
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
OH
READ CYCLE3
(1,4)
t
RC
t
OE
D
OUT
LB,UB
CE
OE
ADDRESS
t
CLZ
(5)
t
ACS
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
READ CYCLE2
(1,3,4)
t
CLZ
t
CHZ
(5)
D
OUT
LB,UB
CE
(5)
t
BA
t
ACS
t
BE
t
BDO
t
BDO
t
BA
t
BE
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