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Revision 1.1
Jan. 2004
1
R0201-BS616LV8010
Very Low Power/Voltage CMOS SRAM
512K X 16 bit
(Single CE Pin)
The BS616LV8010 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.5uA at 3V/25
o
C and maximum access time of 55ns at 3V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV8010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8010 is available in 48B BGA and 44L TSOP2 packages.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
BS616LV8010
1
5
LB
OE
A0
A1
A2
NC
D8
UB
A3
A4
CE
D0
D9
D10
A5
A6
D1
D2
V SS
D11
A17
A7
D3
VCC
V CC
D12
A16
D4
V SS
D14
D13
A 14
A 5
D5
D6
D15
NC
.
A12
A 13
WE
D7
A 8
A 8
A9
A10
A 11
NC
1
A
B
C
D
E
F
G
H
1
2
3
4
6
VSS
Vcc operation voltage : 2.7~3.6V
Very low power consumption :
Vcc = 3.0V C-grade: 30mA (@55ns) operating current
I -grade: 31mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
1.5uA (Typ.) CMOS standby current
High speed access time :
-55 55ns
-70 70ns
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Row
Decoder
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A9 A8 A7
Data
Buffer
Input
Control
Vss
Vcc
OE
WE
CE
D15
D0
A0
A13
A14
A15
A1
A2
16
16
16
16
16
256
4096
2048
22
A17
A16
A10
A12
A6
A11
A3
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A4
A18
48-Ball CSP top View
BSI
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3V
Vcc=3V
Vcc=3V
PKG TYPE
BS616LV8010EC
TSOP2-44
BS616LV8010FC
+0
O
C to +70
O
C
2.7V ~ 3.6V
55 / 70
5uA
30mA
24mA
BGA-48-0912
BS616LV8010EI
TSOP2-44
BS616LV8010FI
-40
O
C to +85
O
C
2.7V ~ 3.6V
55 / 70
10uA
31mA
25mA
BGA-48-0912
55ns
70ns
55ns : 3.0~3.6V
70ns : 2.7~3.6V
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE
A18
A17
A16
A15
A14
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
Vss
Vcc
DQ11
DQ10
DQ9
DQ8
A8
A9
A10
A11
A12
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BS616LV8010EC
BS616LV8010EI
Revision 1.1
Jan. 2004
2
R0201-BS616LV8010
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Vss
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
BS616LV8010
C
IN
Input
Capacitance
V
IN
=0V
10
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
12
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.7V ~ 3.6V
Industrial
-40
O
C to +85
O
C
2.7V ~ 3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0 W
I
OUT
DC Output Current
20
mA
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
MODE
CE
WE
OE
LB
UB
D0~D7
D8~D15
Vcc CURRENT
H
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Not selected
(Power Down)
X
X
X
H
H
High Z
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
X
X
High Z
High Z
I
CC
L
L
Dout
Dout
I
CC
H
L
High Z
Dout
I
CC
Read
L
H
L
L
H
Dout
High Z
I
CC
L
L
Din
Din
I
CC
H
L
X
Din
I
CC
Write
L
L
X
L
H
Din
X
I
CC
L
X
X
H
H
High Z
High Z
I
CC
Revision 1.1
Jan. 2004
3
R0201-BS616LV8010
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
BSI
BS616LV8010
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(3)
Vcc=3.0V
-0.5
--
0.8
V
V
IH
Guaranteed Input High
Voltage
(3)
Vcc=3.0V
2.0
--
Vcc
+
0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
LO
Output Leakage Current
Vcc = Max, CE = V
IH
,
or OE = V
IH
,
V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2mA
Vcc=3.0V
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1mA
Vcc=3.0V
2.4
--
--
V
--
--
31
I
CC
Operating Power Supply
Current
CE = V
IL
,I
DQ
= 0mA
(2)
Vcc=3.0V
--
--
25
mA
I
CCSB
Standby Current
-
TTL
CE = V
IH
,I
DQ
= 0mA
Vcc=3.0V
--
--
1
mA
I
CCSB1
Standby Current
-
CMOS
CE Vcc -0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
Vcc=3.0V
--
1.5
10
uA
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.8 2.5
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
1. Typical characteristics are at TA = 25
o
C. 2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc
_Max.
is 30mA(@55ns) / 24mA(@70ns) during 0~70
o
C operation.
5.I
cc
s
B1
is 5uA at Vcc=3.0V and T
A
=70
o
C.
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
(Max.) is 1.3uA at T
A
=70
O
C.
(4)
(5)
,F = Fmax
55ns
70ns
(3)
Revision 1.1
Jan. 2004
4
R0201-BS616LV8010
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
55
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
--
--
55
ns
t
ELQV
t
ACS
Chip Select Access Time
(CE)
--
--
70
--
--
55
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
--
35
--
--
30
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
35
--
--
30
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE)
10
--
--
10
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z (LB,UB)
5
--
--
5
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE)
--
--
35
--
--
30
ns
t
BDO
t
BDO
Data Byte Control to Output High Z (LB,UB)
--
--
35
--
--
30
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
30
--
--
25
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS616LV8010
(1)
1. t
BA
is 35ns/30ns (@speed=70ns/55ns) with address toggle .
t
BA
is 70ns/55ns (@speed=70ns/55ns) without address toggle .
NOTE :
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
CYCLE TIME : 70ns
MIN. TYP. MAX.
MIN. TYP. MAX.
Vcc = 2.7~3.6V
Vcc = 3.0~3.6V
CYCLE TIME : 55ns
Revision 1.1
Jan. 2004
5
R0201-BS616LV8010
BSI
BS616LV8010
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL .
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
READ CYCLE2
(1,3,4)
READ CYCLE3
(1,4)
t
OH
t
RC
t
OE
D
OUT
LB,UB
CE
OE
ADDRESS
t
CLZ
(5)
t
ACS
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
t
BDO
t
BA
t
BE
t
CLZ
t
CHZ
(5)
D
OUT
LB,UB
CE
(5)
t
BA
t
ACS
t
BE
t
BDO
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