Revision 2.4
April 2002
1
Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BS616LV8022
R0201-BS616LV8022
The BS616LV8022 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8022 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8022 is available in 48-pin BGA type.
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
PRODUCT
FAMILY
PKG TYPE
BS616LV8022BC +0
O
C to +70
O
C
2.4V ~ 5.5V 70 / 100
3uA
30uA
20mA
45mA
BGA-48-0810
BS616LV8022BI -40
O
C to +85
O
C
2.4V ~ 5.5V 70 / 100
6uA
100uA
25mA
50mA
BGA-48-0810
Very low operation voltage : 2.4 ~ 5.5V
Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
High speed access time :
-70 70ns (Max.) at Vcc= 3.0V
-10 100ns (Max.) at Vcc= 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE1, CE2 and OE options
I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
Row
Decoder
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Buffer
Input
Control
Vss
Vdd
OE
WE
CE1
D15
D0
A11
A7
A17
A8
A12
A13
16(8)
16(8)
16(8)
16(8)
16(18)
256(512)
4096
2048
22
A10
A9
A0
A6
A4
A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
A18
PIN CONFIGURATIONS
LB
OE
A0
A1
A2
CE2
D8
UB
A3
A4
CE1
D0
D9
D10
VSS
D3
VCC
VCC
D12
A15
12
A13
WE
D7
A18
A8
A9
A5
A6
D1
D2
D11
A17
A7
A16
D4
VSS
D14
D13
A14
D5
D6
D15
CIO
.
A
A10
A11
SAE.
A
B
C
D
E
F
G
H
1
2
3
4
5
6
VSS
48-Ball CSP top View
OPERATING
TEMPERATURE
Vcc
RANGE
, Max)
Vcc=3V
Vcc=5V
Vcc=3V Vcc=5V
BSI
Vcc=3.0V
Revision 2.4
April 2002
2
BSI
BS616LV8022
R0201-BS616LV8022
PIN DESCRIPTIONS
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
SAE Address Input
This address input incorporate with the above 19 address inputs select one of the
1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
Revision 2.4
April 2002
3
BSI
BS616LV8022
R0201-BS616LV8022
TRUTH TABLE
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
10
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
12
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.4V ~ 5.5V
Industrial
-40
O
C to +85
O
C
2.4V ~ 5.5V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
MODE
CE1
CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
VCC Current
H
X
X
X
Fully Standby
X
L
X
X
X
X
X
High-Z
CCSB
, I
CCSB1
X
High-Z
I
Output Disable
L
H
H
H
X
X
X
X
High-Z
High-Z
I
CC
L
H
Dout
High-Z
H
L
High-Z
Dout
Read from SRAM
( WORD mode )
L
H
L
H
H
L
L
X
Dout
Dout
I
CC
L
H
Din
X
H
L
X
Din
Write to SRAM
( WORD mode )
L
H
X
L
H
L
L
X
Din
Din
I
CC
Read from SRAM
( BYTE Mode )
L
H
L
H
L
X
X
A-1
Dout
High-Z
I
CC
Write to SRAM
( BYTE Mode )
L
H
X
L
L
X
X
A-1
Din
X
I
CC
Revision 2.4
April 2002
4
BSI
BS616LV8022
R0201-BS616LV8022
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
Vcc=3V
-0.5 -- 0.8
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=5V
-0.5 -- 0.8
V
Vcc=3V
2.0 --
Vcc+0.2
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=5V
2.2 --
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1 = V
IH
, or CE2 = V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
-- -- 1
uA
Vcc=3V
-- -- 0.4
V
OL
Output Low Voltage
Vcc= max, I
OL
= 2mA
Vcc=5V
-- -- 0.4
V
Vcc=3V
2.4 -- --
V
OH
Output High Voltage
Vcc= Min, I
OH
= -1mA
Vcc=5V
2.4 -- --
V
Vcc=3V
-- -- 20
I
CC
Operating Power Supply
Current
Vcc= max, CE1 = V
IL
and CE2 =
V
IH
, I
DQ
= 0mA, F = Fmax
(3)
Vcc=5V
-- -- 45
mA
Vcc=3V
-- -- 1
I
CCSB
Standby
Current-TTL
Vcc= max, CE1 = V
IH
or CE2 =
V
IL
, I
DQ
= 0mA
Vcc=5V
-- -- 2
mA
Vcc=3V
-- 0.5 3
I
CCSB1
Standby
Current-CMOS
Vcc= max,CE1
Vcc-0.2V, or
CE2
0.2V; V
IN
Vcc - 0.2V
or V
IN
0.2V
Vcc=5V
-- 3 30
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ t
RC
.
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
Revision 2.4
April 2002
5
BSI
BS616LV8022
R0201-BS616LV8022
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V or CE2
0.2V;
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V or CE2
0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.2 2
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- -- ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- -- ns
1. Vcc = 1.5V, T
A
= + 25
O
C
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to +70
o
C )
2. t
RC
= Read Cycle Time
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE1
Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2
0.2V
Revision 2.4
April 2002
6
BSI
BS616LV8022
R0201-BS616LV8022
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to +70
o
C, Vcc=3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV8022-70
MIN. TYP. MAX.
UNIT
Data Byte Control to Output High Z
Read Cycle Time
t
AVAX
t
AVQV
t
E1LQV
t
GLQV
t
BE
t
EHQZ
t
GHQZ
t
BDO
t
GLQX
t
ELQX
t
BA
t
RC
t
AA
t
ACS1
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
Data Byte Control to Output Low Z
70
10
10
10
0
0
0
10
t
AXQX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable to Output Valid
(CE1)
(CE2,CE1)
70
70
70
35
35
35
35
30
BS616LV8022-10
MIN. TYP. MAX.
100
15
15
15
0
0
0
15
100
100
100
50
50
40
40
35
(CE2,CE1)
ns
t
E2LQV
t
ACS2
(CE2)
Chip Select Access Time
(LB,UB)
(LB,UB)
(LB,UB)
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
100PF
FIGURE 1A
1404
1. t
BA
is 35ns/50ns (@speed=70ns/100ns) with address toggle .
t
BA
is 70ns/100ns (@speed=70ns/100ns) without address toggle .
NOTE :
(1)
Revision 2.4
April 2002
7
BSI
BS616LV8022
R0201-BS616LV8022
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2 = V
IH
.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
t
CHZ
(5)
D
OUT
CE1
(5)
t
ACS1
CE2
t
OH
t
RC
t
OE
D
OUT
LB,UB
CE1
OE
ADDRESS
t
CLZ
(5)
t
ACS1
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
t
BDO
t
BA
t
BE
CE2
t
ACS2
t
ACS2
SWITCHING WAVEFORMS (READ CYCLE)
Revision 2.4
April 2002
8
BSI
BS616LV8022
R0201-BS616LV8022
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to +70
o
C, Vcc=3.0V)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV8022-70
MIN. TYP. MAX.
UNIT
Data Hold from Write Time
Write Cycle Time
t
AVAX
t
E1LWH
t
AVWL
t
WLWH
t
BW
t
DVWH
t
GHQZ
t
WHQX
t
WHDX
t
WLQZ
t
WHAX
t
AVWH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
BW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Output Disable to Output in High Z
End of Write to Output Active
Data Byte Control to End of Write
70
70
0
70
35
0
30
0
30
0
0
5
30
30
ns
ns
(CE2, CE1, WE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
BS616LV8022-10
MIN. TYP. MAX.
100
100
0
100
50
0
40
0
40
0
0
10
40
40
(LB,UB)
WRITE CYCLE1
(1)
SWITCHING WAVEFORMS (WRITE CYCLE)
t
WR
t
WC
(3)
t
CW
(11)
t
BW
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE1
OE
ADDRESS
(5)
CE2
(5)
(5)
LB,UB
(1)
1. t
BW
is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; t
BW
is 70ns/100ns (@speed=70ns/100ns) without address toggle.
NOTE :
Revision 2.4
April 2002
9
BSI
BS616LV8022
R0201-BS616LV8022
t
WC
t
CW
(11)
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE1
ADDRESS
t
DH
(7)
(8)
(8,9)
CE2
LB,UB
t
BW
(5)
(5)
WRITE CYCLE2
(1,6)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. T
WR
is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 2.4
April 2002
10
BSI
BS616LV8022
R0201-BS616LV8022
PACKAGE
B :BGA - 48 PIN(8x10mm)
ORDERING INFORMATION
BS616LV8022
X X -- Y Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
70: 70ns
10: 100ns
PACKAGE DIMENSIONS
48 mini-BGA (8 x 10mm)
E
0.1
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
N E
D
NOTES:
48
10.0
8.0
E1
D1
e
3.75
5.25
0.75
SIDE VIEW
D 0.1
D1
1.4 M
a
x
.
e
E1
0.25
0.05
SOLDER BALL
0.35
0.05
VIEW A
Revision 2.4
April 2002
11
BSI
BS616LV8022
R0201-BS616LV8022
REVISION HISTORY
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
2.3
Modify Standby Current (Typ.
and Max.)
Jun. 29, 2001
2.4
Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 50uA to 100uA.
April,12,2002
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