Revision 2.2
April 2001

R0201-BS616UV1010

POWER DISSIPATION

SPEED

(ns)

STANDBY

CCSB1

, Max)

Operating

, Max)

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=3.0V

Vcc=2.0V

Vcc=3.0V

Vcc=2.0V

PKG TYPE

BS616UV1010EC

TSOP2-44

BS616UV1010AC

C to +70

1.8V ~ 3.6V

150

0.5uA

0.3uA

15mA

10mA

BGA-48-0608

BS616UV1010EI

TSOP2-44

BS616UV1010AI

-40

C to +85

1.8V ~ 3.6V

150

1uA

20mA

1.5uA

15mA

BGA-48-0608

Ultra Low Power/Voltage CMOS SRAM
64K X 16 bit

· Ultra low operation voltage : 1.8 ~ 3.6V
· Ultra low power consumption :

Vcc = 2.0V

C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.01uA (Typ.) CMOS standby current

Vcc = 3.0V

C-grade : 15mA (Max.) operating current

I- grade : 20mA (Max.) operating current

0.02uA (Typ.) CMOS standby current

· High speed access time :

-15

150ns (Max.) at Vcc = 3.0V

· Input levels are CMOS-compatible
· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE and OE options
· I/O Configuration x8/x16 selectable by LB and UB pin

The BS616UV1010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.01uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616UV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin mini-BGA.

DESCRIPTION

FEATURES

Row

Decoder

Memory Array

512 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A3 A2 A1

Data

Input

Buffer

Control

Gnd

Vcc

DQ0

A15

A13

DQ15

128

2048

BLOCK DIAGRAM

512

A14
A12

A11

Address

Input

Buffer

A10

Address Input Buffer

.
.
.
.

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

BS616UV1010

IO15

IO14

IO13

A12

A14

A11

A10

A13

A15

IO5

IO7

IO6

VCC

VSS

IO9

IO12

IO11

IO10

IO4

IO3

IO1

VSS

VCC

IO2

IO8

IO0

A4
A3
A2
A1
A0

DQ0
DQ1
DQ2
DQ3
VCC

GND

DQ4
DQ5

DQ7

DQ6

A15
A14
A13
A12
NC

A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC

1
2
3
4
5

24
23

6
7
8
9
10
11
12
13
14

37
36
35
34
33
32
31
30

BS616UV1010EC
BS616UV1010EI

BSI

Revision 2.2
April 2001

R0201-BS616UV1010

Name

Function

A0-A15 Address Input

These 16 address input select one of the 65,536 x 16-bit words in the RAM.

CE Chip Enable Input

CE is active LOW. Chip enables must be active to read from or write to the device. if
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

DQ0 - DQ15 Data Input/Output

These 16 bi-directional ports are used to read data from or write data into the RAM.

Ports

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

BS616UV1010

MODE

DQ0~DQ7

DQ8~DQ15

Vcc CURRENT

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Read

Dout

High Z

Din

Write

Din

Revision 2.2
April 2001

R0201-BS616UV1010

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

Vcc - 0.2V

Vcc - 0.2V or V

0.2V

1.5

CCDR

Data Retention Current

Vcc -0.2V

Vcc - 0.2V or V

0.2V

0.01

0.2

CDR

Chip Deselect to Data
Retention Time

Operation Recovery Time

See Retention Waveform

(2)

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

1.8V ~ 3.6V

Industrial

-40

C to +85

1.8V ~ 3.6V

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

DATA RETENTION CHARACTERISTICS

( TA = 0

C to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not tested.

DC ELECTRICAL CHARACTERISTICS

( TA = 0

C to + 70

C )

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

BSI

BS616UV1010

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc=2.0V

0.6

Guaranteed Input Low
Voltage

(2)

Vcc=3.0V

-0.5 --

0.8

Vcc=2.0V

1.4

Guaranteed Input High
Voltage

(2)

Vcc=3.0V

2.0

-- Vcc+0.2

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

Output Leakage Current

Vcc = Max, CE = V

, or OE = V

I/O

= 0V to Vcc

-- -- 1 uA

Vcc=2.0V

Output Low Voltage

Vcc = Max, I

= 1mA

Vcc=3.0V

-- -- 0.4 V

Vcc=2.0V

1.6

Output High Voltage

Vcc = Min, I

= -0.5mA

Vcc=3.0V

2.4

-- -- V

Vcc=2.0V

-- -- 10

Operating Power Supply
Current

CE = V

, I

= 0mA, F = Fmax

(3)

Vcc=3.0V

-- -- 15

Vcc=2.0V

-- -- 0.5

CCSB

Standby Current-TTL

CE = V

, I

= 0mA

Vcc=3.0V

-- -- 1

Vcc=2.0V

-- 0.01 0.3

CCSB1

Standby

Current-CMOS

Vcc-0.2V,

Vcc - 0.2V or V

0.2V

Vcc=3.0V

-- 0.02 0.5

Revision 2.2
April 2001

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616UV1010-15

MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

150

AVQV

Address Access Time

150

ELQV

ACS

Chip Select Access Time

(CE)

150

Data Byte Control Access Time

(LB,UB)

150

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

(CE)

Data Byte Control to Output Low Z

(LB,UB)

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

(CE)

BDO

Data Byte Control to Output High Z

(LB,UB)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Output Disable to Output Address Change

R0201-BS616UV1010

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
5ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS ( TA = 0

C to + 70

C, Vcc = 2.0V )

READ CYCLE

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CAR
ANY CHANG
PERMITTED

CHANGE :

STATE

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

LOW V

DATA RETENTION WAVEFORM

( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE Vcc - 0.2V

BSI

BS616UV1010

800

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

90%

Vcc

GND

5ns

90%

10%

1.2V

OUTPUT

FIGURE 2

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

2000

5PF

FIGURE 1B

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

100PF

FIGURE 1A

2000

Revision 2.2
April 2001

R0201-BS616UV1010

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

READ CYCLE3

(1,4)

OUT

LB,UB

ADDRESS

CLZ

(5)

ACS

CHZ

(1,5)

OHZ

(5)

OLZ

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5)

OUT

LB,UB

(5)

ACS

NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

BDO

BSI

BS616UV1010

Revision 2.2
April 2001

R0201-BS616UV1010

AC ELECTRICAL CHARACTERISTICS ( TA = 0

C to + 70

C, Vcc = 2.0V )

WRITE CYCLE

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

(3)

(11)

(2)

OHZ

(4,10)

(3)

OUT

LB,UB

ADDRESS

(5)

BSI

BS616UV1010

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616UV1010-15

MIN. TYP. MAX.

UNIT

AVAX

Write Cycle Time

150

E1LWH

Chip Select to End of Write

150

AVWL

Address Setup Time

AVWH

Address Valid to End of Write

150

WLWH

Write Pulse Width

WHAX

Write recovery Time

(CE,WE)

Date Byte Control to End of Write

(LB,UB)

WLQZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHOX

End of Write to Output Active

Revision 2.2
April 2001

R0201-BS616UV1010

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

(3)

OUT

ADDRESS

(5)

(7)

(8)

(8,9)

LB,UB

BSI

BS616UV1010

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

is measured from the later of CE going low to the end of write.

12. The change of Read/Write cycle must accompany with CE or address toggled.

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