Revision 1.1
Jan. 2004

R0201-BS616UV2019

Ultra Low Power/Voltage CMOS SRAM
128K X 16 bit

· Wide Vcc operation voltage :

C-grade: 1.8V~3.6V

I-grade: 1.9V~3.6V

(Vcc_min.=1.65V at 25

· Ultra low power consumption :

Vcc = 2.0V

C-grade: 8mA (Max.) operating current

I -grade: 10mA (Max.) operating current

0.20uA (Typ.) CMOS standby current

Vcc = 3.0V

C-grade: 11mA (Max.) operating current

I -grade: 13mA (Max.) operating current

0.30uA (Typ.) CMOS standby current

· High speed access time :

-85 85ns (Max.)
-10 100ns (Max.)

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation

The BS616UV2019 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.2uA at 2.0V /25

C and maximum access time of 85ns at 85

Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616UV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV2019 is available in DICE form, JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.

DESCRIPTION

FEATURES

BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor, Inc

. reserves the right to modify document contents without notice.

BS616UV2019

48-ball BGA top view

SPEED

( ns )

STANDBY

( I

CCSB1

, Max )

Operating

( I

, Max )

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

C-grade:1.8~3.6V

Vcc=3.0V

PKG TYPE

BS616UV2019DC

DICE

BS616UV2019TC

TSOP1-48

BS616UV2019AC

C to +70

1.8V ~3.6V

85/100

3.0uA

11mA

BGA-48-0608

BS616UV2019DI

DICE

BS616UV2019TI

TSOP1-48

BS616UV2019AI

-40

C to +85

1.9V ~ 3.6V

85/100

5.0uA

13mA

BGA-48-0608

BSI

Row

Decoder

Memory Array

1024 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A3 A2 A1

Data

Buffer

Input

Control

Gnd

Vcc

CE2,CE

DQ15

DQ0

A16

A15

A13

128

2048

1024

A14
A12

A11

Address

Input

Buffer

A10

Address Input Buffer

.
.
.
.

D15

D14

VSS

VCC

N.C.

D13

A12

A14

D12

D11

D10

A11

A10

A13

A15

A16

N.C.

VSS

VCC

N.C.

A15

A14

A13

A12

A11

A10

/WE

CE2

/UB

/LB

A16

VSS

IO15

IO7

IO14

IO6

IO13

IO5

IO12

IO4

VCC

IO11

IO3

IO10

IO2

IO9

IO1

IO8

IO0

/OE

VSS

/CE

BS616UV2019TC
BS616UV2019TI

Vcc=2.0V

2.0uA

3.0uA

8mA

10mA

· Easy expansion with CE and OE options
· I/O Configuration x8/x16 selectable by LB and UB pin
· Data retention supply voltage as low as 1.0V

I-grade:1.9~3.6V

POWER DISSIPATION

Revision 1.1
Jan. 2004

R0201-BS616UV2019

PIN DESCRIPTIONS

BSI

BS616UV2019

Name

Function

A0-A16 Address Input

These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.

CE Chip Enable 1 Input

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

DQ0 - DQ15 Data Input/Output
Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

CE2 Chip Enable 2 Input

CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

(48B BGA

ignore

CE2

pin)

1. 48B BGA ignore CE2 condition.

MODE

CE2

(1)

D0~D7

D8~D15

Vcc CURRENT

High Z

CCSB

, I

CCSB1

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Read

Dout

High Z

Din

Write

Din

CCSB

, I

CCSB1

High Z

Revision 1.1
Jan. 2004

R0201-BS616UV2019

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE Vcc - 0.2V or CE2 0.2V

(3)

Vcc - 0.2V or V

0.2V

1.0 -- --

CCDR

Data Retention Current

CE Vcc - 0.2V or CE2 0.2V

(3)

Vcc - 0.2V or V

0.2V

-- 0.1 1.0

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

1.8V ~ 3.6V

Industrial

-40

C to +85

1.9V ~ 3.6V

1. Typical characteristics are at T

= 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

4. 48B BGA ignore CE2 condition.

5.I

is 2.0uA/3.0uA at Vcc=2.0V/3.0V and T

=70

6. V

= -1.5V for pulse width less than 30ns

DATA RETENTION CHARACTERISTICS

( TA = -40 to + 85

C )

1. Vcc = 1.0V, T

= + 25

2. t

= Read Cycle Time

3. 48B BGA ignore CE2 condition.

4. Icc

is 0.7uA at T

=70

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not 100% tested.

DC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +85

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

BSI

BS616UV2019

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc=2.0V

0.6

Guaranteed Input Low
Voltage

(2)

Vcc=3.0V

-0.3

0.8

Vcc=2.0V

1.4

Guaranteed Input High
Voltage

(2)

Vcc=3.0V

2.0

Vcc+0.3

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

Output Leakage Current

Vcc = Max, CE = V

, or CE2

(4)

= V

or OE = V

, V

I/O

= 0V to V

Vcc=2.0V

Output Low Voltage

= 0.1mA ; Vcc=Max

Vcc=3.0V

0.4

Vcc=2.0V

Output High Voltage

= -1.0mA ; Vcc=Min

Vcc=3.0V

2.4

Vcc=2.0V

Operating Power Supply
Current

CE = V

= 0mA, F= Fmax

(3)

Vcc=3.0V

Vcc=2.0V

0.1

CCSB

Standby Current TTL

CE = V

, I

= 0mA

Vcc=3.0V

0.5

Vcc=2.0V

0.20

3.0

CCSB1

Standby CurrentCMOS

CE Vcc-0.2V,

Vcc - 0.2V or V

0.2V

Vcc=3.0V

0.30

5.0

CE2 = V

(4)

or CE2 = V

(4)

or CE2 0.2V,

(4)

(5)

(4)

= -0.1mA ; Vcc=Min

= 2.0mA ; Vcc=Max

Vcc-0.2

(6)

0.2

Revision 1.1
Jan. 2004

R0201-BS616UV2019

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

(Vcc = 1.9~3.6V)

UNIT

AVAX

Read Cycle Time

100

AVQV

Address Access Time

100

ELQV

ACS1 , 2

Chip Select Access Time

(CE,CE2)

100

Data Byte Control Access Time

(LB,UB)

GLQV

Output Enable to Output Valid

E1LQX

CLZ

Chip Select to Output Low Z

(CE,CE2)

Data Byte Control to Output Low Z

(LB,UB)

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

(CE,CE2)

BDO

Data Byte Control to Output High Z

(LB,UB)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Data Hold from Address Change

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

READ CYCLE

( 48B BGA ignore CE2 condition)

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

LOW V

DATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.0V

CE Vcc - 0.2V

BSI

BS616UV2019

(1)

1. t

is 50ns/40ns (@speed=100ns/85ns) with address toggle. ; t

is 100ns/85ns (@speed=100ns/85ns) without address toggle.

NOTE :

MIN. TYP. MAX.

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output
Timing Reference Level

0.5Vcc

Output Load

= 100pF+1TTL

= 30pF+1TTL

CYCLE TIME : 100ns

CYCLE TIME : 85ns

Revision 1.1
Jan. 2004

R0201-BS616UV2019

BSI

BS616UV2019

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5,6)

OUT

(5,6)

ACS1

CE2

ACS2(6)

READ CYCLE3

(1,4)

OUT

LB,UB

ADDRESS

CLZ

(5,6)

ACS1

CHZ

(1,5,6)

OHZ

(5)

OLZ

BDO

CE2

ACS2(6)

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V

and CE2 = V

IH.

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

Revision 1.1
Jan. 2004

BSI

BS616UV2019

R0201-BS616UV2019

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

(3)

(11)

(2)

OHZ

(4,10)

(3)

OUT

ADDRESS

(5)

CE2

(5,12)

(5)

LB,UB

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

(Vcc = 1.9~3.6V)

UNIT

AVAX

Write Cycle Time

100

E1LWH

Chip Select to End of Write

100

AVWL

Address Setup Time

AVWH

Address Valid to End of Write

100

WLWH

Write Pulse Width

WHAX

Write recovery Time

(CE,CE2,WE)

Date Byte Control to End of Write

(LB,UB)

WLQZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHOX

End of Write to Output Active

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

WRITE CYCLE

( 48B BGA ignore CE2 condition)

1. t

is 40ns/35ns (@speed=100ns/85ns) with address toggle. ; t

is 100ns/85ns (@speed=100ns/85ns) without address toggle.

(1)

NOTE :

(CE,CE2)

MIN. TYP. MAX.

CYCLE TIME : 100ns

CYCLE TIME : 85ns

Revision 1.1
Jan. 2004

R0201-BS616UV2019

BSI

BS616UV2019

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. The parameter is guaranteed but not 100% tested.
11. T

is measured from the later of CE2 going high or CE going low to the end of write.

12. 48B BGA ignore this parameters related to CE2 .

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

(3)

OUT

ADDRESS

(7)

(8)

(8,9)

CE2

LB,UB

(5)

(5,12)

Revision 1.1
Jan. 2004

R0201-BS616UV2019

ORDERING INFORMATION

BSI

BS616UV2019

PACKAGE DIMENSIONS

48 mini-BGA (6 x 8)

VIEW A

1.4 Max.

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

8.0

6.0

3.75

5.25

NOTES:

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

BS616UV2019 X X

Y Y

GRADE
C: +0

C ~ +70

I: -40

C ~ +85

SPEED
85: 85ns
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free

PACKAGE
T: TSOP1-48
A: BGA-48-0608
D: DICE

Revision 1.1
Jan. 2004

R0201-BS616UV2019

BSI

BS616UV2019

PACKAGE DIMENSIONS

SECTION A-A

BASE METAL

WITH PLATING

c c1

0.0236±0.006

0.020±0.004

0.004 ~ 0.006

0.004 ~ 0.008

0.008±0.001

0.009±0.002

0.0433±0.004

0°~ 8°

0.004 Max.

0.0315±0.004

0.708±0.008

0.472±0.004

0.645±0.004

0.039±0.002

0.004±0.002

"A"

Seating Plane

°
(2

)

°
(2

)

L1
y

SYMBOL

b1
c

UNIT

16.40±0.10

0.50±0.10

0.80±0.10

0.60±0.15

18.00±0.20

11.80±0.10

0°~ 8°

0.1 Max.

0.10 ~ 0.16

0.10 ~ 0.21

0.20±0.03

0.22±0.05

1.00±0.05

0.10±0.05

1.10±0.10

INCH

12°(2x)

"A" DETAIL VIEW

GAUGE PLANE

SEATING PLANE

12°(2x)

0.254

TSOP1-48PIN

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