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Revision 2.2
April 2001
1
R0201-BS616UV8011
BSI
Ultra Low Power/Voltage CMOS SRAM
512K X 16 bit
Ultra low operation voltage : 1.8 ~ 2.3V
Ultra low power consumption :
Vcc = 2.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
High speed access time :
-70 70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE2,CE1 and OE options
I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
FEATURES
Row
Decoder
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A9 A8 A7
Data
Input
Buffer
Control
Gnd
Vcc
OE
A15
A1
16
16
16
16
WE
CE1
D15
D0
A0
A13
A14
A2
16
256
4096
BLOCK DIAGRAM
2048
22
A17
A16
A10
A12
A6
A11
A3
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
BS616UV8011
A4
A18
LB
OE
A0
A1
A2
CE2
D8
UB
A3
A4
CE1
D0
D3
VCC
VCC
D12
A16
D4
VSS
A15
12
A13
WE
D7
D9
D10
A5
A6
D1
D2
VSS
D11
A17
A7
D14
D13
A14
D5
D6
D15
NC
.
A
A 8
A8
A9
A10
A11
NC
1
A
B
C
D
E
F
G
H
1
2
3
4
5
6
VSS
The BS616UV8011 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV8011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8011 is available in 48-pin BGA package.
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
Vcc
RANGE
Vcc=2V
Vcc=2V
PKG TYPE
BS616UV8011DC
DICE
BS616UV8011BC
BGA -48 -0810
BS616UV8011FC
+0
O
C to +70
O
C
1.8 ~ 2.3V
70 / 100
15uA
20mA
BGA -48 -0912
BS616UV8011DI
DICE
BS616UV8011BI
BGA-48 -0810
BS616UV8011FI
-
40
O
C to +85
O
C 1.8 ~ 2.3V
70 / 100
20uA
25mA
BGA-48 -0912
CE2
48-Ball CSP top View
Vcc=2V
OPERATING
TEMPERATURE
PRODUCT FAMILY
POWER DISSIPATION
Revision 2.2
April 2001
2
R0201-BS616UV8011
TRUTH TABLE
PIN DESCRIPTIONS
BSI
BS616UV8011
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
MODE
CE1
CE2
WE
OE
LB
UB
D0~D7
D8~D15
Vcc CURRENT
H
X
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Not selected
(Power Down)
X
L
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
H
X
X
High Z
High Z
I
CC
L
L
Dout
Dout
I
CC
H
L
High Z
Dout
I
CC
Read
L
H
H
L
L
H
Dout
High Z
I
CC
L
L
Din
Din
I
CC
H
L
X
Din
I
CC
Write
L
H
L
X
L
H
Din
X
I
CC
C
IN
Input
Capacitance
V
IN
=0V
10
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
12
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
1.8V ~ 2.3V
Industrial
-40
O
C to +85
O
C
1.8V ~ 2.3V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
Revision 2.2
April 2001
3
R0201-BS616UV8011
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V or CE2 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V or CE2 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.4
10
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
-
n
-
s
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
DC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C )
BSI
BS616UV8011
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE1 Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2
0.2V
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=2V
-0.5
--
0.6
V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=2V
1.4
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1 = V
OE = V , V = 0V to
IH
, or CE2 = V
iL
, or
IH
I/O
Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 1mA
Vcc=2V
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= - 0.5mA
Vcc=2V
1.6
--
--
V
I
CC
Operating Power Supply
Current
Vcc=max, CE1=V
IL
and CE2=
= 0mA, F = Fmax
(3)
Vcc=2V
V
IH
, I
DQ
--
--
20
mA
I
CCSB
Standby Current
-
TTL
Vcc= max, CE1 =V
IH
or CE2 =
V
IL
,I
DQ
= 0mA
Vcc=2V
--
--
0.6
mA
I
CCSB1
Standby Current
-
CMOS
Vcc= max,CE1 Vcc-0.2V, or
CE2
0.2V, V
IN
Vcc - 0.2V
or V
IN
0.2V
Vcc=2V
--
0.6
15
uA
PARAMETER
UNITS
Revision 2.2
April 2001
4
R0201-BS616UV8011
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0 to + 70
o
C, Vcc=2V)
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
CHANGE :
E
STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS616UV8011
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV8011-70
MIN. TYP. MAX.
BS616UV8011-10
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
100
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
--
--
100
ns
t
ELQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
70
--
--
100
ns
t
ELQV
t
ACS2
Chip Select Access Time
(CE2)
--
--
70
--
--
100
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,U )
-
B
-
--
50
--
--
60
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
50
--
--
60
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE2,CE1) 10
--
--
15
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z (LB,UB)
10
--
--
15
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
15
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z (CE2,
0
CE1)
--
35
0
--
40
ns
t
BDO
t
BDO
Data Byte Control to Output High Z (LB,UB)
0
--
30
0
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
30
0
--
35
ns
t
AXOX
t
OH
Output Disable to Address Change
10
--
--
15
--
--
ns
800
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.2V
OUTPUT
FIGURE 2
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
2000
5PF
FIGURE 1B
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
100PF
FIGURE 1A
2000
Revision 2.2
April 2001
5
R0201-BS616UV8011
BSI
BS616UV8011
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2 = V
IH.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
READ CYCLE2
(1,3,4)
t
CLZ
t
CHZ
(5)
D
OUT
CE1
(5)
t
ACS1
CE2
t
ACS2
READ CYCLE3
(1,4)
t
OH
t
RC
t
OE
D
OUT
LB,UB
CE1
OE
ADDRESS
t
CLZ
(5)
t
ACS1
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
t
BDO
t
BA
t
BE
CE2
t
ACS2
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