www.docs.chipfind.ru
Revision 2.4
April 2002
1
BSI
Ultra Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
The BS616UV8020 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.4uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), and active LOW chip enable1(CE1), an active LOW
output enable(OE) and three-state output drivers.
The BS616UV8020 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8020 is available in 48-pin BGA type.
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=2 V
Vcc=2V
Vcc=3V
Vcc=2V
Vcc=3V
PKG TYPE
BS616UV8020BC
+0
O
C to +70
O
C
1.8V ~ 3.6V
70 / 100
2uA
3uA
15mA
20mA
BGA-48-0810
BS616UV8020BI
-40
O
C to +85
O
C
1.8V ~ 3.6V
70 / 100
4uA
6uA
20mA
25mA
BGA-48-0810
Ultra low operation voltage : 1.8 ~3.6V
Ultra low power consumption :
Vcc = 2.0V C-grade: 15mA (Max.) operating current
I-grade : 20mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
High speed access time :
-70 70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE1, CE2 and OE options
I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
BS616UV8020
Row
Decoder
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Buffer
Input
Control
Vss
Vdd
OE
WE
CE1
D15
D0
A11
A7
A17
A8
A12
A13
16(8)
16(8)
16(8)
16(8)
16(18)
256(512)
4096
2048
22
A10
A9
A0
A6
A4
A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
A18
PIN CONFIGURATIONS
R0201-BS616UV8020
LB
OE
A0
A1
A2
CE2
D8
UB
A3
A4
CE1
D0
D9
D10
A5
A6
D1
D2
VSS
D3
VCC
VCC
D12
A16
D4
VSS
A15
D15
CIO
.
A12
A13
WE
D7
D11
A17
A7
D14
D13
A14
D5
D6
A18
A8
A9
A10
A11
SAE.
A
B
C
D
E
F
G
H
1
2
3
4
5
6
VSS
48-Ball CSP top View
Revision 2.4
April 2002
2
PIN DESCRIPTIONS
BSI
BS616UV8020
R0201-BS616UV8020
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM.
SAE Address Input
This address input incorporate with the above 19 address inputs select one of the
1,048,576 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 524,288 x 16-bit words configuration
is selected if CIO is HIGH. 1,048,576 x 8-bit bytes configuration is selected if CIO is
LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
Revision 2.4
April 2002
3
TRUTH TABLE
BSI
BS616UV8020
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
10
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
12
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
1.8V ~ 3.6V
Industrial
-40
O
C to +85
O
C
1.8V ~ 3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +125
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
R0201-BS616UV8020
MODE CE1
CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
VCC
Current
H X
X X
Fully Standby
X L
X X X
X X
X High-Z
High-Z I
CCSB
, I
CCSB1
Output
Disable
L H H H X X X X High-Z
High-Z
I
CC
L H
Dout High-Z
H L
High-Z Dout
Read from SRAM
( WORD mode )
L H L H H
L L
X
Dout Dout
I
CC
L H
Din
X
H L
X
Din
Write to SRAM
( WORD mode )
L H X L H
L L
X
Din Din
I
CC
Read from SRAM
( BYTE Mode )
L H L H L X X A-1 Dout High-Z
I
CC
Write to SRAM
( BYTE Mode )
L H X L L X X A-1 Din
X
I
CC
Revision 2.4
April 2002
4
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
Vcc=2V
-0.5
--
0.6
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=3V
-0.5
--
0.8
V
Vcc=2V
1.4
--
Vcc+0.2
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=3V
2.0
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1 = V
IH
, or CE2 = V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
Vcc=2V
--
--
0.4
V
OL
Output Low Voltage
Vcc= max, I
OL
= 1mA
Vcc=3V
--
--
0.4
V
Vcc=2V
1.6
--
--
V
OH
Output High Voltage
Vcc= Min, I
OH
= -0.5mA
Vcc=3V
2.4
--
--
V
Vcc=2V
--
--
15
I
CC
Operating Power Supply
Current
Vcc=max, CE1=V
IL
and
CE2= V
IH
,I
DQ
= 0mA, F = Fmax
(3)
Vcc=3V
--
--
20
mA
Vcc=2V
--
--
0.6
I
CCSB
Standby Current-TTL
Vcc= max, CE1=V
IH
or CE2 = V
IL
,
I
DQ
= 0mA
Vcc=3V
--
--
1
mA
Vcc=2V
--
0.4
2
I
CCSB1
Standby Current-CMOS
Vcc= max,CE1 Vcc-0.2V, or
CE2 0.2V; V
IN
Vcc - 0.2V
or V
IN
0.2V
Vcc=3V
--
0.5
3
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ t
RC
.
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
BSI
BS616UV8020
R0201-BS616UV8020
Revision 2.4
April 2002
5
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V or CE2
0.2V ;
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V or CE2
0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.2 2
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- -- ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- -- ns
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to +70
o
C )
BSI
BS616UV8020
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE1
Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2
0.2V
R0201-BS616UV8020
PDF 
ZIP