Revision 2.1
Jan.

2004

R0201-BS62LV1605

Very Low Power/Voltage CMOS SRAM
2M X 8 bit

· Vcc operation voltage : 4.5V ~ 5.5V
· Very low power consumption :

Vcc = 5.0V C-grade: 113mA (@55ns) operating current

I -grade: 115mA (@55ns) operating current

C-grade: 90mA (@70ns) operating current

I -grade: 92mA (@70ns) operating current

15uA (Typ.) CMOS standby current

· High speed access time :

-55 55ns
-70 70ns

· Automatic power down when chip is deselected

The BS62LV1605 is a high performance , very low power CMOS Static
Random Access Memory organized as 2048K words by 8 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
15uA at 5.0V/25

C and maximum access time of 55ns at 5.0V/85

Easy memory expansion is provided by an active LOW chip enable (CE1)
, an active HIGH chip enable (CE2) and active LOW output enable (OE)
and three-state output drivers.
The BS62LV1605 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1605 is available in 48B BGA and 44L TSOP2 packages.

GENERAL DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor, Inc

. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

4096 X 4096

Column I/O

Write Driver
Sense Amp

Column Decoder

Data

Buffer

Output

Address Input Buffer

Data

Buffer

Input

Control

Gnd

Vdd

CE2

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

A20
A13
A17
A15
A18
A16
A14
A12

A7
A6
A5
A4

512

4096

A11A9 A8 A3 A2 A1 A0A10 A19

BS62LV1605

POWER DISSIPATION

SPEED

( ns )

STANDBY

( I

CCSB1

, Max )

Operating

( I

, Max )

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=5V

PKG TYPE

BS62LV1605EC

TSOP2-44

BS62LV1605FC

C to +70

4.5V ~ 5.5V

55 / 70

110uA

113mA

90mA

BGA-48-0912

BS62LV1605EI

TSOP2-44

BS62LV1605FI

-40

C to +85

4.5V ~ 5.5V

55 / 70

220uA

115mA

92mA

BGA-48-0912

A4
A3
A2
A1
A0

CE1

NC
NC

DQ0
DQ1

VCC

GND

DQ2
DQ3

NC
A20
WE

A19
A18
A17
A16
A15

A5
A6
A7
OE
CE2
A8
NC
NC
DQ7
DQ6
GND
VCC
DQ5
DQ4
NC
NC
A9
A10
A11
A12
A13
A14

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

BS62LV1605EC
BS62LV1605EI

CE1

BSI

· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE1, CE2 and OE options

55ns

70ns

55ns : 4.5~5.5V
70ns : 4.5~5.5V

A11

A10

A18

A19

A12

A14

A13

A15

A20

VSS

A17

A16

VCC

VSS

VCC

CE2

CE1

48-ball BGA top view

Revision 2.1
Jan.

2004

R0201-BS62LV1605

Name

Function

A0-A20 Address Input

These 21 address inputs select one of the 2048K x 8-bit words in the RAM

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0-DQ7 Data Input/Output
Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not 100% tested.

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +85

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

BS62LV1605

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial 0

C to +70

4.5V ~ 5.5V

Industrial -40

C to +85

4.5V ~ 5.5V

MODE

CE1

CE2

I/O OPERATION

Vcc CURRENT

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Read

OUT

Write

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Revision 2.1
Jan.

2004

R0201-BS62LV1605

1. Typical characteristics are at TA = 25

C. 2. Fmax = 1/t

3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc

_Max.

is 113mA(@55ns) / 90mA(@70ns) during 0~70

C operation.

5. I

is 110uA at Vcc=5.0V and T

=70

DATA RETENTION CHARACTERISTICS

( TA = -40 to + 85

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

3. I

(Max.) is 2.5uA at T

=70

DC ELECTRICAL CHARACTERISTICS

( TA = -40

C to + 85

C )

BSI

LOW V

DATA RETENTION WAVEFORM (1)

( CE1 Controlled )

CE1

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE1 Vcc - 0.2V

BS62LV1605

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE1 Vcc - 0.2V or CE2 0.2V,
V

Vcc - 0.2V or V

0.2V

1.5 -- --

CCDR

(3)

Data Retention Current

CE1 Vcc - 0.2V or CE2 0.2V,
V

Vcc - 0.2V or V

0.2V

1.5 5

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low
Voltage

(3)

Vcc=5V

-0.5 -- 0.8 V

Guaranteed Input High
Voltage

(3)

Vcc=5V

2.2 --

Vcc+0.3

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

-- -- 1 uA

Output Leakage Current

Vcc = Max, CE1 = V

or CE2 = V

OE = V

, V

I/O

= 0V to Vcc

-- -- 1 uA

Output Low Voltage

Vcc = Max, I

= 2mA

Vcc=5V

-- -- 0.4 V

Output High Voltage

Vcc = Min, I

= -1mA

Vcc=5V

2.4

-- -- V

55ns

-- -- 115

(4)

Operating Power Supply
Current

CE1= V

, CE2= V

IH,

= 0mA, F = Fmax

(2)

70ns

Vcc=5V

-- -- 92

CCSB

Standby

Current-TTL

CE1

or CE2= V

IL,

= 0mA

Vcc=5V

-- -- 2.5 mA

CCSB1

(5)

Standby

Current-CMOS

CE1Vcc-0.2V or CE20.2V,
V

Vcc - 0.2V or V

0.2V

Vcc=5V

15 220

LOW V

DATA RETENTION WAVEFORM (2)

( CE2 Controlled )

CE2

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE2 0.2V

Revision 2.1
Jan.

2004

JEDEC

PARAMETER

NAME

DESCRIPTION

UNIT

AVAX

Read Cycle Time

AVQV

Address Access Time

E1LQV

ACS1

Chip Select Access Time (CE1)

E2LQV

ACS2

Chip Select Access Time (CE2)

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Data Hold from Address Change

R0201-BS62LV1605

AC ELECTRICAL CHARACTERISTICS

( TA = -40

C to + 85

C )

READ CYCLE

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS62LV1605

PARAMETER

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output
Timing Reference Level

0.5Vcc

Output Load

= 30pF+1TTL

= 100pF+1TTL

MIN. TYP. MAX.

Vcc=4.5~5.5V

MIN. TYP. MAX.

Vcc=4.5~5.5V

CYCLE TIME : 70ns

CYCLE TIME : 55ns

Revision 2.1
Jan.

2004

R0201-BS62LV1605

SWITCHING WAVEFORMS (READ CYCLE

)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V

and CE2 = V

3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = V

5. The parameter is guaranteed but not 100% tested.

BSI

BS62LV1605

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5)

OUT

CE1

(5)

ACS1

CE2

ACS2

READ CYCLE3

(1,4)

OUT

CE1

ADDRESS

CLZ

(5)

ACS1

CHZ

(1,5)

OHZ

(5)

OLZ

CE2

ACS2

Revision 2.1
Jan.

2004

R0201-BS62LV1605

AC ELECTRICAL CHARACTERISTICS

( TA = -40

C to + 85

C )

WRITE CYCLE

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

BSI

BS62LV1605

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

UNIT

AVAX

Write Cycle Time

E1LWH

Chip Select to End of Write

AVWL

Address Set up Time

AVWH

Address Valid to End of Write

WLWH

Write Pulse Width

WHAX

Write Recovery Time (CE2,CE1 , WE)

WLOZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHOZ

OHZ

Output Disable to Output in High Z

WHQX

End of Write to Output Active

(3)

(11)

(2)

OHZ

(4,10)

(3)

OUT

CE1

ADDRESS

(5)

CE2

(5)

MIN. TYP. MAX.

(Vcc=4.5~5.5V)

CYCLE TIME : 70ns

CYCLE TIME : 55ns

Revision 2.1
Jan.

2004

R0201-BS62LV1605

WRITE CYCLE2

(1,6)

BSI

BS62LV1605

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. The parameter is guaranteed but not 100% tested.
11. T

is measured from the later of CE2 going high or CE1 going low to the end of write.

(11)

(2)

WHZ

(4,10)

(3)

OUT

CE1

ADDRESS

(7)

(8)

(8,9)

CE2

(5)

Revision 2.1
Jan.

2004

ORDERING INFORMATION

BSI

PACKAGE DIMENSIONS

BS62LV1605

R0201-BS62LV1605

TSOP2-44

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

BS62LV1605 X X

Y Y

GRADE
C: +0

C ~ +70

I: -40

C ~ +85

SPEED
55: 55ns
70: 70ns

PKG MATERIAL
-: Normal
G: Green
P: Pb free

PACKAGE
E: TSOP2-44
F: BGA-48-0912

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