R0201-BS62LV2001

Revision 2.5
April 2002

PIN CONFIGURATIONS

A17

Very Low Power/Voltage CMOS SRAM
256K X 8 bit

· Wide Vcc operation voltage : 2.4V ~ 5.5V
· Very low power consumption :

Vcc = 3.0V

C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.1uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade : 35mA (Max.) operating current

I- grade : 40mA (Max.) operating current

0.6uA (Typ.) CMOS standby current

· High speed access time :

-70 70ns(Max.) at Vcc = 3.0V
-10

100ns(Max.) at Vcc = 3.0V

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE2, CE1, and OE options
· All I/O pins are 3V/5V tolerant

FEATURES

The BS62LV2001 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.

DESCRIPTION

BLOCK DIAGRAM

PRODUCT FAMILY

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

Address

Input

Buffer

Row

Decoder

Memory Array

1024 x 2048

Column I/O

Sense Amp

Write Driver

Column Decoder

Data

Buffer

Output

Address Input Buffer

A8 A3 A2 A1

A10

Data

Buffer

Input

Control

Gnd

Vdd

DQ7

DQ6

DQ5

DQ4

A16

A15

DQ3

DQ2

DQ1

DQ0

A5
A4

A13

256

2048

1024

A14
A12

BS62LV2001

A11

CE1

CE2

BSI

OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3

A11

A9
A8

A13

CE2

A15

VCC

A17
A16
A14
A12

A7
A6
A5
A4

BS62LV2001TC
BS62LV2001STC
BS62LV2001TI
BS62LV2001STI

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A17
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

GND

VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3

BS62LV2001SC
BS62LV2001SI

32
31
30
29
28
27
26
25
24
23
22
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17

R0201-BS62LV2001

Revision 2.5
April 2002

R0201-BS62LV2001

Name

Function

A0-A17 Address Input

These 18 address inputs select one of the 262,144 x 8-bit words in the RAM

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

DQ0 DQ7 Data Input/Output
Ports

These 8 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

BS62LV2001

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

2.4V ~ 5.5V

Industrial

-40

C to +85

2.4V ~ 5.5V

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not tested.

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

MODE

CE1

CE2

I/O OPERATION

Vcc CURRENT

Not selected

(Power Down)

CCSB

, I

CCSB1

High Z

Output Disabled

High Z

Read

OUT

Write

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

R0201-BS62LV2001

Revision 2.5
April 2002

BSI

BS62LV2001

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE1

Vcc - 0.2V, CE2

0.2V,

Vcc - 0.2V or V

0.2V

1.5 -- --

CCDR

Data Retention Current

CE1

Vcc - 0.2V, CE2

0.2V,

Vcc - 0.2V or V

0.2V

-- 0.01 0.5

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc=3.0V

Guaranteed Input Low
Voltage

(2)

Vcc=5.0V

-0.5 -- 0.8 V

Vcc=3.0V

2.0

Guaranteed Input High
Voltage

(2)

Vcc=5.0V

2.2

-- Vcc+0.2

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

Output Leakage Current

Vcc = Max, CE1= V

, CE2= V

IL,

OE = V

, V

I/O

= 0V to Vcc

-- -- 1 uA

Vcc=3.0V

Output Low Voltage

Vcc = Max, I

= 2mA

Vcc=5.0V

-- -- 0.4 V

Vcc=3.0V

Output High Voltage

Vcc = Min, I

= -1mA

Vcc=5.0V

2.4 -- -- V

Vcc=3.0V

-- -- 20

Operating Power Supply
Current

CE1 = V

, or CE2 = V

= 0mA, F = Fmax

(3)

Vcc=5.0V

-- -- 35

Vcc=3.0V

-- -- 1

CCSB

Standby

Current-TTL

CE1 = V

, or CE2 = V

= 0mA, F = Fmax

(3)

Vcc=5.0V

-- -- 2

Vcc=3.0V

-- 0.1 0.7

CCSB1

Standby

Current-CMOS

CE1 Vcc-0.2V, CE2 0.2V,
V

Vcc-0.2V or V

0.2V

Vcc=5.0V

-- 0.6 6

1. Typical characteristics are at TA = 25

3. Fmax = 1/t

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

DATA RETENTION CHARACTERISTICS

( TA = 0

C to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

DC ELECTRICAL CHARACTERISTICS

( TA = 0

C to + 70

C )

LOW V

DATA RETENTION WAVEFORM (1)

( CE1 Controlled )

CE1

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE1 Vcc - 0.2V

LOW V

DATA RETENTION WAVEFORM (2)

( CE2 Controlled )

CE2

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE2

0.2V

R0201-BS62LV2001

Revision 2.5
April 2002

R0201-BS62LV2001

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62LV2001-70

MIN. TYP. MAX.

BS62LV2001-10

MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

100

AVQV

Address Access Time

100

E1LQV

ACS1

Chip Select Access Time

(CE1)

100

E2HOV

ACS2

Chip Select Access Time

(CE2)

100

GLQV

Output Enable to Output Valid

E1LQX

CLZ1

Chip Select to Output Low Z

(CE1)

E2HOX

CLZ2

Chip Select to Output Low Z

(CE2)

GLQX

OLZ

Output Enable to Output in Low Z

E1HQZ

CHZ1

Chip Deselect to Output in High Z

(CE1)

E2HQZ

CHZ1

Chip Deselect to Output in High Z

(CE2)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Output Disable to Output Address Change

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
5ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS

( TA = 0

C to + 70

C, Vcc = 3.0V )

READ CYCLE

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CAR
ANY CHANG
PERMITTED

CHANGE :

STATE

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS62LV2001

667

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

90%

Vcc

GND

5ns

90%

10%

1.73V

OUTPUT

FIGURE 2

3.3V

OUTPUT

INCLUDING
JIG AND
SCOPE

1269

1404

5PF

FIGURE 1B

3.3V

INCLUDING
JIG AND
SCOPE

1269

100PF

FIGURE 1A

1404

OUTPUT

R0201-BS62LV2001

Revision 2.5
April 2002

R0201-BS62LV2001

NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = V

and CE2= V

IH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V

5. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

BSI

BS62LV2001

READ CYCLE3

(1,4)

READ CYCLE2

(1,3,4)

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

CLZ

(5)

OUT

CE2

CE1

(5)

ACS2

ACS1

CLZ2

CHZ2

(2,5)

OUT

CE2

CE1

ADDRESS

(5)

CLZ1

(5)

ACS1

ACS2

CHZ1

(1,5)

OHZ

(5)

OLZ

CHZ1

, t

CHZ2

R0201-BS62LV2001

Revision 2.5
April 2002

R0201-BS62LV2001

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS62LV2001-70

MIN. TYP. MAX.

BS62LV2001-10

MIN. TYP. MAX.

UNIT

AVAX

Write Cycle Time

100

E1LWH

Chip Select to End of Write

100

AVWL

Address Set up Time

AVWH

Address Valid to End of Write

100

WLWH

Write Pulse Width

WHAX

WR1

Write Recovery Time

(CE1 , WE)

E2LAX

WR2

Write Recovery Time

(CE2)

WLOZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHOZ

OHZ

Output Disable to Output in High Z

WHQX

End of Write to Output Active

AC ELECTRICAL CHARACTERISTICS

( TA = 0

C to + 70

C, Vcc = 3.0V )

WRITE CYCLE

SWITCHING WAVEFORMS (WRITE CYCLE)

BSI

BS62LV2001

WRITE CYCLE1

(1)

WR1

(3)

(11)

(2)

OHZ

(4,10)

WR2

(3)

OUT

CE2

CE1

ADDRESS

(5)

R0201-BS62LV2001

Revision 2.5
April 2002

BSI

BS62LV2001

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

WR2

(3)

OUT

CE2

CE1

ADDRESS

(5)

(7)

(8)

(8,9)

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.

All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.

3. T

is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the

outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input

signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

11. T

is measured from the later of CE1 going low or CE2 going high to the end of write.

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