R0201-BS62LV2008
Revision 1.1
Jan. 2004
1
A17
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
Vcc operation voltage : 4.5V ~ 5.5V
Very low power consumption :
Vcc = 5.0V C-grade: 53mA (@55ns) operating current
I -grade: 55mA (@55ns) operating current
C-grade: 43mA (@70ns) operating current
I -grade: 45mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
High speed access time :
-55 55ns
-70 70ns
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE2, CE1, and OE options
The BS62LV2008 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0u
A
at 5.0
V
/25
o
C
and maximum access time of 55ns at 5.0
V
/ 85
o
C
.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2008 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2008 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
A8 A3 A2 A1
A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A16
A5
A4
A6
A7
A15
A13
8
8
8
8
16
256
2048
1024
20
A14
A12
A9
BS62LV2008
A11
A0
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
BS62LV2008TC
BS62LV2008STC
BS62LV2008TI
BS62LV2008STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
WE
CE1
CE2
BSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
BS62LV2008SC
BS62LV2008SI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=5.0V
Vcc=5.0V
PKG TYPE
BS62LV2008DC
DICE
BS62LV2008TC
TSOP-32
BS62LV2008STC
STSOP-32
BS62LV2008SC
+0
O
C to +70
O
C
4.5V ~5.5V
55/70
10uA 43mA
SOP-32
BS62LV2008DI
DICE
BS62LV2008TI
TSOP-32
BS62LV2008STI
STSOP-32
BS62LV2016SI
-40
O
C to +85
O
C
4.5V ~ 5.5V
55/70
30uA
45mA
SOP-32
55ns
70ns
53mA
55mA
55ns: 4.5~5.5V
70ns: 4.5~5.5V
R0201-BS62LV2008
Revision 1.1
Jan. 2004
2
Name
Function
A0-A17 Address Input
These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial 0
O
C to +70
O
C
4.5V ~ 5.5V
Industrial -40
O
C to +85
O
C
4.5V ~ 5.5V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
X
H
X
X
Not selected
(Power Down)
X
X
L
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
H
High Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
BS62LV2008
SYMBOL
PARAMETER
CONDITIONS
UNIT
MAX.
R0201-BS62LV2008
Revision 1.1
Jan. 2004
3
BSI
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1 Vcc - 0.2V or CE2 0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
(3)
Data Retention Current
CE1 Vcc - 0.2V or CE2 0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.1 1.0
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
1. Typical characteristics are at T
A
= 25
o
C. 2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I
cc
s
B1
_Max.
is 10uA at Vcc=5.0V and T
A
=70
o
C.
5. Icc
_Max.
is 53mA(@55ns) /43mA(@70ns) at Vcc=5.0V and T
A
=0~70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. Icc
DR_MAX.
is 0.7uA at T
A
=70
o
C.
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE1 Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2 0.2V
BS62LV2008
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(3)
Vcc=5.0V
-0.5 -- 0.8 V
V
IH
Guaranteed Input High
Voltage
(3)
Vcc=5.0V
2.2 --
V
cc
+0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
-- -- 1 uA
I
LO
Output Leakage Current
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
-- -- 1 uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2.0mA
Vcc=5.0V
-- -- 0.4 V
V
OH
Output High Voltage
Vcc = Min,
I
OH
= -1.0mA
Vcc=5.0V
2.4 -- -- V
70ns
45
I
CC
(5)
Operating Power Supply
Current
CE1 = V
IL
, CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(2)
5.0 V
55ns
-- --
55
mA
I
CCSB
Standby
Current-TTL
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA,
Vcc=5.0V
-- -- 1.0
mA
I
CCSB1
(4)
Standby
Current-CMOS
CE1Vcc-0.2V or CE20.2V,
V
IN
Vcc-0.2V or V
IN
0.2V
Vcc=5.0V
-- 1.0 30 uA
R0201-BS62LV2008
Revision 1.1
Jan. 2004
4
AC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C)
READ CYCLE
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS62LV2008
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
(Vcc = 4.5~5.5V)
(Vcc = 4.5~5.5V)
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
E1LQV
t
ACS1
Chip Select Access Time
--
--
55
--
--
70
ns
t
E2HOV
t
ACS2
--
--
55
--
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
10
--
--
10
--
--
ns
t
E2HOX
t
CLZ2
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
--
--
30
--
--
35
ns
t
E2HQZ
t
CHZ2
--
--
30
--
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
MIN. TYP. MAX.
MIN. TYP. MAX.
Chip Select Access Time
(CE2)
(CE1)
Chip Select to Output Low Z
(CE1)
(CE2)
Chip Deselect to Output in High Z
(CE1)
(CE2)
CYCLE TIME : 55ns
CYCLE TIME : 70ns
R0201-BS62LV2008
Revision 1.1
Jan. 2004
5
BSI
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
t
CLZ
(5)
D
OUT
CE2
CE1
(5)
t
ACS2
t
ACS1
t
OH
t
RC
t
OE
t
CLZ2
t
CHZ2
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
(5)
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ1
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
t
CHZ1,
t
CHZ2
BS62LV2008
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
R0201-BS62LV2008
Revision 1.1
Jan. 2004
6
BSI
BS62LV2008
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
t
WR1
t
WC
(3)
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
AC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
(Vcc = 4.5~5.5V)
UNIT
t
AVAX
t
WC
Write Cycle Time
55
--
--
70
--
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
55
--
--
70
--
--
ns
t
AVWL
t
AS
Address Setup Time
0
--
--
0
--
--
ns
t
AVWH
t
AW
Address Valid to End of Write
55
--
--
70
--
--
ns
t
WLWH
t
WP
Write Pulse Width
30
--
--
35
--
--
ns
t
WHAX
t
WR1
Write recovery Time
(CE1,WE)
0
--
--
0
--
--
ns
t
E2LAX
t
WR2
(CE2)
0
--
--
0
--
--
ns
t
WLQZ
t
WHZ
Write to Output in High Z
--
--
25
--
--
30
ns
t
DVWH
t
DW
Data to Write Time Overlap
25
--
--
30
--
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
--
0
--
--
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t
WHOX
t
OW
End of Write to Output Active
5
--
--
5
--
--
ns
MIN. TYP. MAX.
MIN. TYP. MAX.
Write recovery Time
CYCLE TIME : 70ns
R0201-BS62LV2008
Revision 1.1
Jan. 2004
7
BSI
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. T
WR
is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7.
D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE1 going low or CE2 going high to the end of write.
WRITE CYCLE2
(1,6)
t
WC
t
CW
(11)
(11)
t
CW
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
WR2
(3)
t
DH
t
DW
D
IN
D
OUT
WE
CE2
CE1
ADDRESS
(5)
(5)
t
OW
(7)
(8)
(8,9)
BS62LV2008
R0201-BS62LV2008
Revision 1.1
Jan. 2004
8
ORDERING INFORMATION
BSI
PACKAGE DIMENSIONS
STSOP - 32
BS62LV2008
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
D: DICE
BS62LV2008 X X
Z
Y Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
R0201-BS62LV2008
Revision 1.1
Jan. 2004
9
BSI
PACKAGE DIMENSIONS (continued)
TSOP - 32
BS62LV2008
BASE METAL
WITH PLATING
c c1
SECTION A-A
b1
b
SOP -32
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