Very Low Power CMOS SRAM
32K X 8 bit

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

Pb-Free and Green package materials are compliant to RoHS

FEATURES

Wide V

operation voltage : 2.4V ~ 5.5V

Very low power consumption :
V

= 3.0V Operation current : 25mA (Max.) at 70ns

1mA (Max.) at 1MHz

Standby current : 0.01uA(Typ.) at 25

= 5.0V Operation current : 40mA (Max.) at 55ns

2mA (Max.) at 1MHz

Standby current : 0.4uA (Typ.) at 25

High speed access time :
-55

55ns(Max.) at V

4.5~5.5V

-70

70ns(Max.) at V

3.0~5.5V

Automatic power down when chip is deselected

Easy expansion with CE and OE options

Three state outputs and TTL compatible

Fully static operation

Data retention supply voltage as low as 1.5V

DESCRIPTION

The BS62LV256 is a high performance, very low power CMOS Static
Random Access Memory organized as 32,768 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.01uA and maximum access time of 70ns in 3.0V
operation.
Easy memory expansion is provided by an active LOW chip enable
(CE), and active LOW output enable (OE) and three-state output
drivers.
The BS62LV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV256 is available in DICE form, JEDEC standard 28 pin
330mil Plastic SOP, 600mil Plastic DIP, 8mmx13.4mm TSOP
(normal type).

POWER CONSUMPTION

POWER DISSIPATION

STANDBY

CCSB1

, Max)

Operating

, Max)

=5.0V

=3.0V

PRODUCT

FAMILY

OPERATING

TEMPERATURE

=5.0V V

=3.0V

1MHz

10MHz

Max.

1MHz

10MHz

Max.

PKG TYPE

BS62LV256DC

DICE

BS62LV256PC

PDIP-28

BS62LV256SC

SOP-28

BS62LV256TC

Commercial

C to +70

1.0uA

0.2uA

1.5mA

18mA

35mA

0.8mA

12mA

20mA

TSOP-28

BS62LV256PI

PDIP-28

BS62LV256SI

SOP-28

BS62LV256TI

Industrial

-25

C to +85

2.0uA

0.4uA

2mA

20mA

40mA

1mA

15mA

25mA

TSOP-28

PIN CONFIGURATIONS

BLOCK DIAGRAM

Brilliance Semiconductor, Inc.

reserves the right to change products and specifications without notice.

1
2
3
4
5
6
7
8
9
10
11
12
13
14

A14
A12

A7
A6
A5
A4
A3
A2
A1
A0

DQ0
DQ1
DQ2

GND

VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3

28
27
26
25
24
23
22
21
20
19
18
17
16
15

BS62LV256PC
BS62LV256PI
BS62LV256SC
BS62LV256SI

�

Address

Input

Buffer

Row

Decoder

Memory Array

512X512

Column I/O

Write Driver

Sense Amp

Column Decoder

Address Input Buffer

A3 A2 A1 A0 A10

Data

Input

Buffer

Control

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

A5
A6
A7

A12
A14
A13

A8
A9

A11

512

GND

Data

Output

Buffer

A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2

1
2
3
4
5
6
7
8
9
10
11
12
13
14

A11

A9
A8

A13

VCC

A14
A12

A7
A6
A5
A4
A3

BS62LV256TC
BS62LV256TI

28
27
26
25
24
23
22
21
20
19
18
17
16
15

�

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

PIN DESCRIPTIONS

Name

Function

A0-A14 Address Input

These 15 address inputs select one of the 32,768 x 8-bit in the RAM

CE Chip Enable Input

CE is active LOW. Chip enable must be active when data read form or write to the
device. If chip enable is not active, the device is deselected and is in standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

DQ0-DQ7 Data Input/Output
Ports

There 8 bi-directional ports are used to read data from or write data into the RAM.

Power Supply

GND

Ground

TRUTH TABLE

MODE

I/O OPERATION

CURRENT

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Read

OUT

Write

NOTES: H means V

; L means V

; X means don

t care (Must be V

or V

state)

ABSOLUTE MAXIMUM RATINGS

(1)

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5

(2)

to 7.0

BIAS

Temperature Under
Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

1. Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

�

2.0V in case of AC pulse width less than 30 ns.

OPERATING RANGE

RANG

AMBIENT

TEMPERATURE

Commercial

C to + 70

2.4V ~ 5.5V

Industrial

-25

C to + 85

2.4V ~ 5.5V

CAPACITANCE

(1)

= 25

C, f = 1.0MHz)

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

Input
Capacitance

= 0V

Input/Output
Capacitance

I/O

= 0V

1. This parameter is guaranteed and not 100% tested.

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

DC ELECTRICAL CHARACTERISTICS (T

= -25

C to +85

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN.

TYP.

(1)

MAX.

UNITS

Power Supply

2.4

5.5

Input Low Voltage

-0.5

(2)

0.8

Input High Voltage

2.2

+0.3

(3)

Input Leakage Current

= 0V to V

Output Leakage Current

CE= V

, or OE = V

I/O

= 0V to V

Output Low Voltage

= Max, I

= 0.5mA

0.4

Output High Voltage

= Min, I

= -0.5mA

2.4

=3.0V

(5)

Operating Power Supply
Current

CE = V

= 0mA, f = F

MAX

(4)

=5.0V

=3.0V

CC1

Operating Power Supply
Current

CE = V

= 0mA, f = 1MHz

=5.0V

=3.0V

1.0

CCSB

Standby Current

�

TTL

CE = V

= 0mA

=5.0V

2.0

=3.0V

0.01

0.4

CCSB1

(6)

Standby Current

�

CMOS

-0.2V,

-0.2V or V

0.2V

=5.0V

0.4

2.0

1. Typical characteristics are at T

=25

C and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V

+1.0V in case of pulse width less than 20 ns.

4. F

MAX

=1/t

RC.

5. I

CC (MAX.)

is 20mA/35mA at V

=3.0V/5.0V and T

=70

6. I

CCSB1(MAX.)

is 0.2uA/1.0uA at V

=3.0V/5.0V and T

=70

DATA RETENTION CHARACTERISTICS (T

= -25

C to +85

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.

(1)

MAX.

UNITS

for Data Retention

-0.2V,

-0.2V or V

0.2V

1.5

CCDR

(3)

Data Retention Current

-0.2V,

-0.2V or V

0.2V

0.01

0.4

CDR

Chip Deselect to Data
Retention Time

Operation Recovery Time

See Retention Waveform

(2)

1. V

=1.5V, T

=25

C and not 100% tested.

2. t

= Read Cycle Time.

3. I

CCDR(Max.)

is 0.2uA at T

=70

LOW V

DATA RETENTION WAVEFORM (CE Controlled)

Data Retention Mode

CDR

- 0.2V

1.5V

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output Timing
Reference Level

0.5Vcc

CLZ

, t

OLZ

, t

CHZ

, t

OHZ

, t

WHZ

= 5pF+1TTL

Output Load

Others

100pF+1TTL

1. Including jig and scope capacitance.

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM

WILL BE CHANGE
FROM

MAY CHANGE
FROM

WILL BE CHANGE
FROM

DON

T CARE

ANY CHANGE
PERMITTED

CHANGE :
STATE UNKNOW

DOES NOT
APPLY

CENTER LINE IS
HIGH INPEDANCE

OFF

STATE

AC ELECTRICAL CHARACTERISTICS (T

= -25

C to +85

READ CYCLE

CYCLE TIME : 55ns

= 4.5~5.5V)

CYCLE TIME : 70ns

= 3.0~5.5V)

JEDEC

PARAMETER

NAME

PARANETER

NAME

DESCRIPTION

MIN.

TYP. MAX. MIN.

TYP. MAX.

UNITS

AVAX

Read Cycle Time

AVQX

Address Access Time

E1LQV

ACS

Chip Select Access Time

GLQV

Output Enable to Output Valid

E1LQX

CLZ

Chip Select to Output Low Z

GLQX

OLZ

Output Enable to Output Low Z

E1HQZ

CHZ

Chip Select to Output High Z

GHQZ

OHZ

Output Enable to Output High Z

AVQX

Data Hold from Address Change

(1)

1 TTL

Output

ALL INPUT PULSES

90%

GND

Rise Time :
1V/ns

Fall Time :
1V/ns

90%

10%

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1

(1,2,4)

READ CYCLE 2

(1,3,4)

READ CYCLE 3

(1, 4)

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. Transition is measured

�

500mV from steady state with C

= 5pF.

The parameter is guaranteed but not 100% tested.

CLZ

(5)

OUT

ACS

CHZ

(5)

OUT

ADDRESS

CLZ

(5)

ACS

CHZ

(1,5)

OHZ

(5)

OLZ

OUT

ADDRESS

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

AC ELECTRICAL CHARACTERISTICS (T

= -25

C to +85

WRITE CYCLE

CYCLE TIME : 55ns

= 4.5~5.5V)

CYCLE TIME : 70ns

= 3.0~5.5V)

JEDEC

PARAMETER

NAME

PARANETER

NAME

DESCRIPTION

MIN.

TYP. MAX. MIN.

TYP. MAX.

UNITS

AVAX

Write Cycle Time

AVWH

Address Valid to End of Write

E1LWH

Chip Select to End of Write

WLWH

Write Pulse Width

AVWL

Address Set up Time

WHAX

Write Recovery Time

(CE, WE)

WLQZ

WHZ

Write to Output High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHQX

End of Write to Output Active

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1

(1)

(3)

(11)

(2)

OHZ

(4,10)

OUT

ADDRESS

(5)

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

WRITE CYCLE 2

(1,6)

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive. The
data input setup and hold timing should be referenced to the second transition edge of the
signal that terminates the write.

3. t

is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to

the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured

�

500mV from steady state with C

= 5pF.

The parameter is guaranteed but not 100% tested.

11. t

is measured from the later of CE going low to the end of write.

(11)

(2)

WHZ

(4,10)

OUT

(7)

(8)

(8,9)

ADDRESS

(5)

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

ORDERING INFORMATION

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.

PACKAGE DIMENSIONS

BASE METAL

WITH PLATING

SOP - 28

0.020

�

0.005X45

�

PACKAGE
D: DICE

S: SOP
T: TSOP (8mm x 13.4mm)
P: PDIP

BS62LV256

X X Z Y Y

GRADE
C: +0

C ~ +70

I: -25

C ~ +85

SPEED
55: 55ns
70: 70ns

PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant

BS62LV256

R0201-BS62LV256

Revision

2.4

Jan.

2006

PACKAGE DIMENSIONS (continued)

"A"

0.004 ~ 0.006

0.004 ~ 0.008

0.0045

�

0.0026

0.0315

�

0.004

0.0197

0.022

�

0.004

0.008

�

0.001

�

~ 8

�

0.004 Max.

0.528

�

0.008

0.315

�

0.004

0.465

�

0.004

0.009

�

0.002

0.039

�

0.002

0.0433

�

0.004

INCH

SYMBOL

UNIT

0.10 ~ 0.16

0.80

�

0.10

�

~ 8

�

0.1 Max.

0.55

�

0.10

11.80

�

0.10

0.50

13.40

�

0.20

8.00

�

0.10

- 0.004

+0.008

- 0.10

+0.20

0.115

�

0.065

0.10 ~ 0.21

0.20

�

0.03

0.22

�

0.05

1.00

�

0.05

1.10

�

0.10

TSOP - 28

WITH PLATING

SECTION A-A

BASE METAL

�

SEATING PLANE

"A" DATAIL VIEW

Seating Plane

�

(2x)

�

(2x)

GAUGE PLANE

0.254

�

(2x)

�

(2x)

PDIP - 28

Электронный компонент: BS62LV256PCP70