Revision 2.2
April. 2001
1
R0201-BS62LV4000
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
Wide Vcc operation voltage : 2.7V ~ 3.6V
Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I -grade: 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
High speed access time :
-70 70ns (Max) at Vcc = 3.0V
-10 100ns (Max) at Vcc = 3.0V
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE and OE options
The BS62LV4000 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.5uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
The BS62LV4000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4000 is available in the JEDEC standard 32 pin
, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
2048 X 2048
Column I/O
Sense Amp
Write Driver
Column Decoder
Data
Buffer
Output
Address Input Buffer
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE
DQ5
DQ4
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
8
8
8
8
DQ7
DQ6
DQ3
DQ2
DQ1
DQ0
16
256
2048
2048
22
A11 A9 A8 A3 A2 A1 A0 A10
BS62LV4000
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS62LV4000TC
TSOP-32
BS62LV4000STC
+0
O
C to +70
O
C
2.7V ~ 3.6V
70 / 100
8uA
20mA
STSOP-32
BS62LV4000TI
TSOP-32
BS62LV4000STI
-40
O
C to +85
O
C
2.7V ~ 3.6V
70 / 100
12uA
25mA
STSOP-32
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
BS62LV4000TC
BS62LV4000STC
BS62LV4000TI
BS62LV4000STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BSI
Revision 2.2
April. 2001
2
R0201-BS62LV4000
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input
CE is active LOW. Chip enable must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
These 8 bi-directional ports are used to read data from or write data into the
Ports
RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
MODE
WE
CE
OE
I/O OPERATION
Vcc CURRENT
Not selected
SB1
X
H
X
High Z
I
CCSB
, I
CC
Output Disabled
H
L
H
High Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
C
-40 to +125
O
T
STG
Storage Temperature
C
-60 to +150
O
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
mA
20
BS62LV4000
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.7V ~ 3.6V
Industrial
-40
O
C to +85
O
C
2.7V ~ 3.6V
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
Revision 2.2
April. 2001
3
R0201-BS62LV4000
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0 to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
BSI
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
BS62LV4000
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE
Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE
Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.3
6
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=3.0V
-0.5 -- 0.8 V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=3.0V
2.0 --
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
-- -- 1 uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2mA
Vcc=3.0V
-- -- 0.4 V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1mA
Vcc=3.0V
2.4
-- -- V
I
CC
Operating Power Supply
Current
CE = V
IL
, I
DQ
= 0mA, F = Fmax
(3)
Vcc=3.0V
-- -- 20 mA
I
CCSB
Standby Current-TTL
CE = V
IH
, I
DQ
= 0mA
Vcc=3.0V
-- -- 1 mA
I
CCSB1
Standby
Current-CMOS
CE
Vcc-0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
Vcc=3.0V
-- 0.5 8 uA
Revision 2.2
April. 2001
4
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62LV4000-70
MIN. TYP. MAX.
BS62LV4000-10
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
--
100
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
70
--
--
100
ns
t
ELQV
t
ACS
Chip Select Access Time
--
--
70
--
--
100
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
50
--
--
60
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
10
--
--
15
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
15
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
0
--
30
0
-
3
-
5
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
25
0
-
3
-
0
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
15
--
--
ns
R0201-BS62LV4000
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C , Vcc = 3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
CHANGE :
E
STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS62LV4000
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
1404
5PF
FIGURE 1B
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
100PF
FIGURE 1A
1404
Revision 2.2
April. 2001
5
R0201-BS62LV4000
SWITCHING WAVEFORMS (READ CYCLE
)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
BSI
t
CLZ
t
CHZ
(5)
D
OUT
CE
(5)
t
ACS
t
OH
t
RC
t
OE
D
OUT
CE
OE
ADDRESS
t
CLZ
(5)
t
ACS
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
BS62LV4000
Revision 2.2
April. 2001
6
R0201-BS62LV4000
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C , Vcc = 3.0V )
WRITE CYCLE
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1
(1)
BSI
t
WR
(3)
t
CW
(11)
(2)
t
WP
t
AW
t
OHZ
(4,10)
t
AS
t
DH
t
DW
D
IN
D
OUT
WE
CE
OE
ADDRESS
(5)
t
WC
BS62LV4000
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS62LV4000-70
MIN. TYP. MAX.
BS62LV4000-10
MIN. TYP. MAX.
UNIT
t
AVAX
t
WC
Write Cycle Time
70
--
--
100
--
--
ns
t
E1LWH
t
CW
Chip Select to End of Write
70
--
--
100
--
--
ns
t
AVWL
t
AS
Address Set up Time
0
--
--
0
--
--
ns
t
AVWH
t
AW
Address Valid to End of Write
70
--
--
100
--
--
ns
t
WLWH
t
WP
Write Pulse Width
50
--
--
70
--
--
ns
t
WHAX
t
WR
Write Recovery Time
(CE , WE)
0
--
--
0
--
--
ns
t
WLOZ
t
WHZ
Write to Output in High Z
0
--
30
0
--
40
ns
t
DVWH
t
DW
Data to Write Time Overlap
35
--
--
40
--
--
ns
t
WHDX
t
DH
Data Hold from Write Time
0
--
--
0
--
--
ns
t
GHOZ
t
OHZ
Output Disable to Output in High Z
0
--
30
0
--
40
ns
t
WHQX
t
OW
End ot Write to Output Active
5
--
--
10
--
--
ns
Revision 2.2
April. 2001
7
R0201-BS62LV4000
WRITE CYCLE2
(1,6)
BSI
t
WC
t
CW
(11)
(2)
t
WP
t
AW
t
WHZ
(4,10)
t
AS
t
DH
t
DW
D
IN
D
OUT
WE
CE
ADDRESS
(5)
t
DH
(7)
(8)
(8,9)
BS62LV4000
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR
is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE going low to the end of write.
Revision 2.2
April. 2001
8
PACKAGE
T: TSOP
ST: Small TSOP
ORDERING INFORMATION
BSI
BS62LV4000
X X
Y Y
GRADE
C: +0
o
C ~ +70
o
C
I: -40
o
C ~ +85
o
C
SPEED
70: 70ns
10: 100ns
PACKAGE DIMENSIONS
BS62LV4000
R0201-BS62LV4000
STSOP - 32
Revision 2.2
April. 2001
9
BSI
BS62LV4000
R0201-BS62LV4000
PACKAGE DIMENSIONS (continued)
TSOP - 32
Revision 2.2
April. 2001
10
BSI
R0201-BS62LV4000
REVISION HISTORY
Revision
Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
BS62LV4000
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