ADS7820
1
FEATURES
q
100kHz min SAMPLING RATE
q
0 to +5V INPUT RANGE
q
72dB min SINAD WITH 45kHz INPUT
q
1/2 LSB max INL AND DNL
q
SINGLE +5V SUPPLY OPERATION
q
PIN-COMPATIBLE WITH 16-BIT ADS7821
q
USES INTERNAL OR EXTERNAL
REFERENCE
q
COMPLETE WITH S/H, REF, CLOCK, ETC.
q
FULL PARALLEL DATA OUTPUT
q
100mW max POWER DISSIPATION
q
28-PIN 0.3" PLASTIC DIP AND SOIC
ADS7820
DESCRIPTION
The ADS7820 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit, capacitor-based SAR A/D with S/H,
reference, clock, interface for microprocessor use, and
three-state output drivers.
The ADS7820 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide a 0 to +5V input
range, with power dissipation under 100mW.
The 28-pin ADS7820 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial 40
C to +85
C range.
12-Bit 10
s Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
Successive Approximation Register and Control Logic
Clock
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
BUSY
Comparator
BYTE
CS
R/C
CDAC
Internal
+2.5V Ref
Buffer
4k
0 to +5V Input
REF
CAP
5k
20k
6.66k
ADS7820
ADS7820
1996 Burr-Brown Corporation
PDS-1322
Printed in U.S.A. June, 1996
2
ADS7820
SPECIFICATIONS
ELECTRICAL
T
A
= 40
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference, unless otherwise specified.
ADS7820P/U
ADS7820PB/UB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
Guaranteed
RESOLUTION
12
D
Bits
ANALOG INPUT
Voltage Ranges
0 to +5
D
V
Impedance
10
D
k
Capacitance
35
D
pF
THROUGHPUT SPEED
Conversion Time
5.7
8
D
D
s
Complete Cycle
Acquire and Convert
10
D
s
Throughput Rate
100
D
kHz
DC ACCURACY
Integral Linearity Error
1.0
0.5
LSB
(1)
Differential Linearity Error
1.0
0.5
LSB
No Missing Codes
D
Bits
Transition Noise
(2)
0.1
D
LSB
Full Scale Error
(3,4)
0.5
0.25
%
Full Scale Error Drift
7
5
ppm/
C
Full Scale Error
(3,4)
Ext. 2.5000V Ref
0.5
0.25
%
Full Scale Error Drift
Ext. 2.5000V Ref
2
D
ppm/
C
Offset Error
8
4
mV
Offset Error Drift
2
D
ppm/
C
Power Supply Sensitivity
+4.75V < V
D
< +5.25V
0.75
0.5
LSB
(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
Spurious-Free Dynamic Range
f
IN
= 45kHz
80
D
dB
(5)
Total Harmonic Distortion
f
IN
= 45kHz
80
D
dB
Signal-to-(Noise+Distortion)
f
IN
= 45kHz
70
72
dB
Signal-to-Noise
f
IN
= 45kHz
70
72
dB
Full-Power Bandwidth
(6)
250
D
kHz
SAMPLING DYNAMICS
Aperture Delay
40
D
ns
Transient Response
FS Step
2
D
s
Overvoltage Recovery
(7)
150
D
ns
REFERENCE
Internal Reference Voltage
2.48
2.5
2.52
D
D
D
V
Internal Reference Source Current
1
D
A
(Must use external buffer.)
External Reference Voltage Range
2.3
2.5
2.7
D
D
D
V
for Specified Linearity
External Reference Current Drain
Ext. 2.5000V Ref
100
D
A
DIGITAL INPUTS
Logic Levels
V
IL
0.3
+0.8
D
D
V
V
IH
+2.0
V
D
+0.3V
D
D
V
I
IL
10
D
A
I
IH
10
D
A
DIGITAL OUTPUTS
Data Format
Parallel 12 bits
Data Coding
Straight Binary
V
OL
I
SINK
= 1.6mA
+0.4
D
V
V
OH
I
SOURCE
= 500
A
+4
D
V
Leakage Current
High-Z State,
5
D
A
V
OUT
= 0V to V
DIG
Output Capacitance
High-Z State
15
D
pF
DIGITAL TIMING
Bus Access Time
83
D
ns
Bus Relinquish Time
83
D
ns
ADS7820
3
POWER SUPPLIES
Specified Performance
V
DIG
Must be
V
ANA
+4.75
+5
+5.25
D
D
D
V
V
ANA
+4.75
+5
+5.25
D
D
D
V
+I
DIG
0.3
D
mA
+I
ANA
16
D
mA
Power Dissipation
f
S
= 100kHz
100
D
mW
TEMPERATURE RANGE
Specified Performance
40
+85
D
D
C
Derated Performance
55
+125
D
D
C
Storage
65
+150
D
D
C
Thermal Resistance (
JA
)
Plastic DIP
75
D
C/W
SOIC
75
D
C/W
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, 0 to +5V input ADS7820, one LSB is 1.22mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 4b. (4) Full scale error is the worst case of Full Scale untrimmed deviation from
ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Full-
Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified
performance after 2 x FS input overvoltage.
SPECIFICATIONS
(CONT)
ELECTRICAL
T
A
= 40
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference, unless otherwise specified.
ADS7820P/U
ADS7820PB/UB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: V
IN
.................................................... 0.7V to +V
ANA
+0.3V
REF .................................... +V
ANA
+0.3V to AGND2 0.3V
CAP ........................................... Indefinite Short to AGND2
Momentary Short to V
ANA
Ground Voltage Differences: DGND, AGND1, AGND2 ...................
0.3V
V
ANA
....................................................................................................... 7V
V
DIG
to V
ANA
..................................................................................... +0.3V
V
DIG
....................................................................................................... 7V
Digital Inputs ............................................................ 0.3V to +V
DIG
+0.3V
Maximum Junction Temperature ................................................... +165
C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300
C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER
(1)
ADS7820P
Plastic DIP
246
ADS7820PB
Plastic DIP
246
ADS7820U
SOIC
217
ADS7820UB
SOIC
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
MINIMUM
SIGNAL-TO-
MAXIMUM
(NOISE +
SPECIFICATION
LINEARITY
DISTORTION)
TEMPERATURE
PRODUCT
ERROR (LSB)
RATIO (dB)
RANGE
PACKAGE
ADS7820P
1.0
70
40
C to +85
C
Plastic DIP
ADS7820PB
0.5
72
40
C to +85
C
Plastic DIP
ADS7820U
1.0
70
40
C to +85
C
SOIC
ADS7820UB
0.5
72
40
C to +85
C
SOIC
ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
4
ADS7820
1
V
IN
Analog Input. Full-scale input range is 0 to +5V.
2
AGND1
Analog Ground. Used internally as ground reference point.
3
REF
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both
cases, connect to ground with a 2.2
F Tantalum capacitor.
4
CAP
Reference Buffer Capacitor. 2.2
F Tantalum to ground.
5
AGND2
Analog Ground.
6
D11 (MSB)
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D10
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
D9
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D8
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
D7
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
11
D6
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
12
D5
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
13
D4
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
14
DGND
Digital Ground.
15
D3
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
16
D2
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
17
D1
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
18
D0 (LSB)
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
19
DZ
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
20
DZ
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
21
DZ
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
22
DZ
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
23
BYTE
Byte Select. With BYTE LOW, data will be output as indicated above, causing pin 6 (D11) to output the MSB, and pin 18 (D0) to
output the LSB. Pins 19 to 22 will output LOWs. With BYTE HIGH, the top and bottom 8 bits of data will be switched, so that pin 6
outputs data bit 3, pin 9 outputs data bit 0 (LSB), pin 10 to 13 output LOWs, pin 15 outputs data bit 11 (MSB) and pin 22 outputs
data bit 4.
24
R/C
Read/Convert input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
With CS LOW, a rising edge on R/C enables the output data bits.
25
CS
Chip Select. Internally OR'd with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge
on CS will enable the output data bits.
26
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to
latch the data. CS or R/C must be high when BUSY rises, or another conversion will start, without time for signal acquisition.
27
V
ANA
Analog Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1
F ceramic and 10
F Tantalum
capacitors.
28
V
DIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be
V
ANA
.
PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
DZ
DZ
DZ
DZ
D0 (LSB)
D1
D2
D3
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7820
PIN #
NAME
DESCRIPTION
PIN ASSIGNMENTS
ADS7820
5
ADS7820 AT +25C
0.2
+0.1
0
0.1
0.2
0
512
1024
1536
2048
2560
3072
3584
4096
Decimal Code
12-Bit LSBs
Min/Max DNL Errors
0.073 at 00512
0.087 at 02047
TYPICAL PERFORMANCE CURVES
At T
A
= 40
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference, unless otherwise specified.
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.52
2.515
2.51
2.505
2.5
2.495
2.49
2.485
2.48
40
15
10
35
60
85
Temperature (C)
Internal Reference (V)
CONVERSION TIME vs TEMPERATURE
6.2
6.1
6
5.9
5.8
5.7
5.6
5.5
5.4
40
15
10
35
60
85
Temperature (C)
Conversion Time (s)
ADS7820 AT +25C
0.2
+0.1
0
0.1
0.2
0
512
1024
1536
2048
2560
3072
3584
4096
Decimal Code
12-Bit LSBs
Min/Max INL Errors
0.051 at 03962
0.086 at 02048
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