1
ADS7821
FEATURES
q
100kHz min SAMPLING RATE
q
0 to +5V INPUT RANGE
q
86dB min SINAD WITH 20kHz INPUT
q
DNL: 16-bits "No Missing Codes"
q
SINGLE +5V SUPPLY OPERATION
q
PIN-COMPATIBLE WITH 12-BIT ADS7820
q
USES INTERNAL OR EXTERNAL
REFERENCE
q
FULL PARALLEL DATA OUTPUT
q
100mW max POWER DISSIPATION
q
28-PIN 0.3" PLASTIC DIP AND SOIC
ADS7821
DESCRIPTION
The ADS7821 is a complete 16-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 16-bit, capacitor-based, SAR A/D with S/H,
reference, clock, interface for microprocessor use, and
three-state output drivers.
The ADS7821 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide a 0 to +5V input
range, with power dissipation under 100mW.
The 28-pin ADS7821 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the 25
C to +85
C range.
16-Bit 10
s Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
Successive Approximation Register and Control Logic
Clock
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
BUSY
Comparator
BYTE
CS
R/C
CDAC
Internal
+2.5V Ref
Buffer
4k
0 to +5V Input
REF
CAP
5k
20k
6.66k
1996 Burr-Brown Corporation
PDS-1323A
Printed in U.S.A. June, 1996
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
ADS7821
ADS7821
2
ADS7821
SPECIFICATIONS
ELECTRICAL
T
A
= 25
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= V
D
= +5V, using external reference, unless otherwise specified.
ADS7821P, U
ADS7821PB, UB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
Parallel 16 bits
Straight Binary
RESOLUTION
16
D
Bits
ANALOG INPUT
Voltage Range
0 to +5
D
V
Impedance
10
D
k
Capacitance
35
D
pF
THROUGHPUT SPEED
Conversion Cycle
Acquire and Convert
10
D
s
Throughput Rate
100
D
kHz
DC ACCURACY
Integral Linearity Error
4
3
LSB
(1)
No Missing Codes
15
16
Bits
Transition Noise
(2)
0.9
D
LSB
Full Scale Error
(3,4)
0.5
0.25
%
Full Scale Error Drift
2
D
ppm/
C
Full Scale Error
(3,4)
Internal Reference
0.5
0.25
%
Full Scale Error Drift
Internal Reference
7
5
ppm/
C
Offset Error
8
4
mV
Offset Error Drift
2
D
ppm/
C
Power Supply Sensitivity
+4.75V < V
D
< +5.25V
12
8
LSB
(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
Spurious-Free Dynamic Range
f
IN
= 20kHz
90
94
dB
(5)
Total Harmonic Distortion
f
IN
= 20kHz
90
94
dB
Signal-to-(Noise+Distortion)
f
IN
= 20kHz
83
86
dB
f
IN
= 60dB Input
28
30
dB
Signal-to-Noise
f
IN
= 20kHz
83
86
dB
Full-Power Bandwidth
(6)
250
D
kHz
SAMPLING DYNAMICS
Aperture Delay
40
D
ns
Transient Response
FS Step
2
D
s
Overvoltage Recovery
(7)
150
D
ns
REFERENCE
Internal Reference Voltage
2.48
2.5
2.52
D
D
D
V
Internal Reference Source Current
1
D
A
(Must use external buffer)
Internal Reference Drift
8
D
ppm/
C
External Reference Voltage Range
2.3
2.5
2.7
D
D
D
V
for Specified Linearity
External Reference Current Drain
Ext. 2.5000V Ref
100
D
A
DIGITAL INPUTS
Logic Levels
V
IL
0.3
+0.8
D
D
V
V
IH
+2.0
V
D
+0.3V
D
D
V
I
IL
10
D
A
I
IH
10
D
A
DIGITAL OUTPUTS
Data Format
Data Coding
V
OL
I
SINK
= 1.6mA
+0.4
D
V
V
OH
I
SOURCE
= 500
A
+4
D
V
Leakage Current
High-Z State,
5
D
A
V
OUT
= 0V to V
DIG
Output Capacitance
High-Z State
15
D
pF
DIGITAL TIMING
Bus Access Time
83
D
ns
Bus Relinquish Time
83
D
ns
3
ADS7821
POWER SUPPLIES
Specified Performance
V
DIG
Must be
V
ANA
+4.75
+5
+5.25
D
D
D
V
V
ANA
+4.75
+5
+5.25
D
D
D
V
I
DIG
0.3
D
mA
I
ANA
16
D
mA
Power Dissipation
f
S
= 100kHz
100
D
mW
TEMPERATURE RANGE
Specified Performance
25
+85
D
D
C
Derated Performance
55
+125
D
D
C
Storage
65
+150
D
D
C
Thermal Resistance (
JA
)
Plastic DIP
75
D
C/W
SOIC
75
D
C/W
NOTES: (1) LSB means Least Significant Bit. For the 16-bit, 0 to +5V input ADS721, one LSB is 76
V. (2) Typical rms noise at worst case transitions and
temperatures. (3) Adjustable to zero with external potentiometer as shown in Figure 6a. (4) Full scale error is the worst case of Full Scale untrimmed deviation from
ideal last code transition divided by the transition voltage and includes the effect of offset error. (5) All specifications in dB are referred to a full-scale input. (6) Full-
Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified
performance after 2 x FS input overvoltage.
SPECIFICATIONS
(CONT)
ELECTRICAL
T
A
= 25
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= V
D
= +5V, using external reference, unless otherwise specified.
ADS7821P, U
ADS7821PB, UB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ABSOLUTE MAXIMUM RATINGS
Analog Inputs: V
IN
...................................................... 0.7V to V
ANA
+0.3V
REF ................................... AGND2 0.3V to +V
ANA
+0.3V
CAP .......................................... Indefinite Short to AGND2,
Momentary Short to V
ANA
Ground Voltage Differences: DGND, AGND1, AGND2 ...................
0.3V
V
ANA
....................................................................................................... 7V
V
DIG
to V
ANA
..................................................................................... +0.3V
V
DIG
....................................................................................................... 7V
Digital Inputs ............................................................ 0.3V to +V
DIG
+0.3V
Maximum Junction Temperature ................................................... +165
C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300
C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER
(1)
ADS7821P
Plastic DIP
246
ADS7821PB
Plastic DIP
246
ADS7821U
SOIC
217
ADS7821UB
SOIC
217
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
MINIMUM
SIGNAL-TO-
MAXIMUM
(NOISE +
SPECIFICATION
LINEARITY
DISTORTION)
TEMPERATURE
PRODUCT
ERROR (LSB)
RATIO (dB)
RANGE
PACKAGE
ADS7821P
4
83
25
C to +85
C
Plastic DIP
ADS7821PB
3
86
25
C to +85
C
Plastic DIP
ADS7821U
4
83
25
C to +85
C
SOIC
ADS7821UB
3
86
25
C to +85
C
SOIC
ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
4
ADS7821
1
V
IN
Analog Input.
2
AGND1
Analog Ground. Used internally as ground reference point.
3
REF
Reference Input/Output. 2.2
F tantalum capacitor to ground.
4
CAP
Reference Buffer Capacitor. 2.2
F tantalum capacitor to ground.
5
AGND2
Analog Ground.
6
D15 (MSB)
O
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D14
O
Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
D13
O
Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D12
O
Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
D11
O
Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW.
11
D10
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
12
D9
O
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
13
D8
O
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
14
DGND
Digital Ground.
15
D7
O
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
16
D6
O
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
17
D5
O
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
18
D4
O
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
19
D3
O
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
20
D2
O
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
21
D1
O
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
22
D0 (LSB)
O
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
23
BYTE
I
Swaps Pins 6 through 13 with Pins 15 through 22 when HIGH. See Figures 2 and 5.
24
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
25
CS
I
Internally OR'd with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
26
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
V
ANA
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1
F ceramic and 10
F tantalum capacitors.
28
V
DIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be
V
ANA
.
DIGITAL
PIN #
NAME
I/O
DESCRIPTION
TABLE I. Pin Assignments.
PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
V
IN
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7821
5
ADS7821
+1.0
+0.5
0.5
1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
16-Bit LSBs
Min/Max DNL Errors
0.740 at 36431
1.070 at 32767
+2.0
+1.0
1.0
2.0
16-Bit LSBs
Min/Max INL Errors
0.900 at 12447
1.910 at 32767
0
8192 16384 24576 32768 40960 49152 57344 65536
TYPICAL PERFORMANCE CURVES
T
A
= 25
C to +85
C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using external reference, unless otherwise specified.
2.52
2.515
2.51
2.505
2.5
2.495
2.49
2.485
2.48
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
Temp (C)
25
0
25
50
75
Internal Reference (V)
8.00
7.90
7.80
7.70
7.60
7.50
7.40
7.30
7.20
CONVERSION TIME vs TEMPERATURE
Temp (C)
25
0
25
50
75
Conversion Time (s)
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