Burr Brown Products
from Texas Instruments
FEATURES
APPLICATIONS
DESCRIPTION
CDAC
_
+
Output
Latches
and
3-State
Drivers
BYTE
16-/8-Bit
Parallel DATA
Output Bus
SAR
Conversion
and
Control Logic
Comparator
Clock
+IN
-IN
REFIN
CONVST
BUSY
CS
RD
RESET
4.096-V
Internal
Reference
REFOUT
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
16-BIT, 2 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
DWDM
2-MHz Sample Rate
Instrumentation
16-Bit NMC Ensured Over Temperature
High-Speed, High-Resolution, Zero Latency
Zero Latency
Data Acquisition Systems
Unipolar Single-Ended Input Range:
Transducer Interface
0 V to V
ref
Medical Instruments
Onboard Reference
Communication
Onboard Reference Buffer
High-Speed Parallel Interface
Power Dissipation: 175 mW at 2 MHz Typ
The ADS8411 is a 16-bit, 2 MHz A/D converter with
Wide Digital Supply
an internal 4.096-V reference. The device includes a
16-bit capacitor-based SAR A/D converter with in-
8-/16-Bit Bus Transfer
herent sample and hold. The ADS8411 offers a full
48-Pin TQFP Package
16-bit interface and an 8-bit option where data is read
ESD Sensitive HBM Capability of 500 V,
using two 8-bit read cycles.
1000 V at All Input Pins
The ADS8411 has a unipolar single-ended input. It is
available
in
a
48-lead
TQFP
package
and
is
characterized over the industrial -40
C to 85
C tem-
perature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20022004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUM
NO MISSING
PACKAGE
TEMPERA-
TRANSPORT
INTEGRAL
DIFFERENTIAL
CODES
PACKAGE
ORDERING
MODEL
DESIG-
TURE
MEDIA
LINEARITY
LINEARITY
RESOLUTION
TYPE
INFORMATION
NATOR
RANGE
QUANTITY
(LSB)
(LSB)
(BIT)
Tape and reel
ADS8411IPFBT
250
48 Pin
ADS8411I
6 ~ 6
2~3
15
PFB
40
C to 85
C
TQFP
Tape and reel
ADS8411IPFBR
1000
Tape and reel
ADS8411IBPFBT
250
48 Pin
ADS8411IB
2.5 ~ 2.5
1~2
16
PFB
40
C to 85
C
TQFP
Tape and reel
ADS8411IBPFBR
1000
(1)
For the most current specifications and package information, refer to our website at www.ti.com.
over operating free-air temperature range unless otherwise noted
(1)
UNIT
+IN to AGND
0.4 V to +VA + 0.1 V
Voltage
IN to AGND
0.4 V to 0.5 V
+VA to AGND
0.3 V to 7 V
Voltage range
+VBD to BDGND
0.3 V to 7 V
+VA to +VBD
0.3 V to 2.55 V
Digital input voltage to BDGND
0.3 V to +VBD + 0.3 V
Digital output voltage to BDGND
0.3 V to +VBD + 0.3 V
T
A
Operating free-air temperature range
40
C to 85
C
T
stg
Storage temperature range
65
C to 150
C
Junction temperature (T
J
max)
150
C
Power dissipation
(T
J
Max - T
A
)/
JA
TQFP package
JA
thermal impedance
86
C/W
Vapor phase (60 sec)
215
C
Lead temperature, soldering
Infrared (15 sec)
220
C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SPECIFICATIONS
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
T
A
= 40
C to 85
C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage
(1)
+IN (IN)
0
V
ref
V
+IN
0.2
V
ref
+ 0.2
Absolute input voltage
V
IN
0.2
0.2
Input capacitance
25
pF
Input leakage current
0.5
nA
SYSTEM PERFORMANCE
Resolution
16
Bits
ADS8411I
15
No missing codes
Bits
ADS8411IB
16
ADS8411I
6
4
6
INL
Integral linearity
(2) (3)
LSB
ADS8411IB
2.5
1.5
2.5
ADS8411I
2
1
3
DNL
Differential linearity
LSB
ADS8411IB
1
0.8
2
ADS8411I
1.5
0.5
1.5
mV
E
O
Offset error
(4)
ADS8411IB
0.75
0.25
0.75
mV
ADS8411I
0.15
0.15
E
G
Gain error
(4) (5)
%FS
ADS8411IB
0.098
0.098
Noise
60
V RMS
At FFFFh output code,
PSRR
DC Power supply rejection ratio
+VA = 4.75 V to 5.25 V,
2
LSB
V
ref
= 4.096 V
(4)
SAMPLING DYNAMICS
Conversion time
340
400
ns
Acquisition time
100
ns
Throughput rate
2
MHz
Aperture delay
2
ns
Aperture jitter
25
ps
Step response
100
ns
Overvoltage recovery
100
ns
DYNAMIC CHARACTERISTICS
V
IN
= 4 V
pp
at 100 kHz
90
dB
THD
Total harmonic distortion
(6)
V
IN
= 4 V
pp
at 500 kHz
88.5
dB
SNR
Signal-to-noise ratio
V
IN
= 4 V
pp
at 100 kHz
86
dB
SINAD
Signal-to-noise + distortion
V
IN
= 4 V
pp
at 100 kHz
85
dB
V
IN
= 4 V
pp
at 100 kHz
90
dB
SFDR
Spurious free dynamic range
V
IN
= 4 V
pp
at 500 kHz
88
dB
-3dB Small signal bandwidth
5
MHz
EXTERNAL VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, V
ref
3.9
4.096
4.2
V
Reference resistance
(7)
500
k
(1)
Ideal input span, does not include gain or offset error.
(2)
LSB means least significant bit
(3)
This is endpoint INL, not best fit.
(4)
Measured relative to an ideal full-scale input [+IN (IN)] of 4.096 V
(5)
This specification does not include the internal reference voltage error and drift.
(6)
Calculated on the first nine harmonics of the input frequency
(7)
Can vary
20%
3
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ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
SPECIFICATIONS (continued)
T
A
= 40
C to 85
C, +VA = 5 V, +VBD = 3 V or 5 V, V
ref
= 4.096 V, f
SAMPLE
= 2 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
From 95% (+VA), with 1
Internal reference start-up time
120
ms
F storage capacitor
V
ref
Reference voltage
IOUT = 0
4.065
4.096
4.13
V
Source current
Static load
10
A
Line regulation
+VA = 4.75 ~ 5.25 V
0.6
mV
Drift
IOUT = 0
36
PPM/
C
DIGITAL INPUT/OUTPUT
Logic family -- CMOS
V
IH
High level input voltage
I
IH
= 5 A
+VBD 1
+VBD + 0.3
V
IL
Low level input voltage
I
IL
= 5 A
0.3
0.8
V
V
OH
High level output voltage
I
OH
= 2 TTL loads
+VBD 0.6
+VBD
V
OL
Low level output voltage
I
OL
= 2 TTL loads
0
0.4
Data format -- straight binary
POWER SUPPLY REQUIREMENTS
+VBD
2.7
3
5.25
V
Power supply voltage
+VA
4.75
5
5.25
V
+VA Supply current
(8)
f
s
= 2 MHz
35
38
mA
P
D
Power dissipation
(8)
f
s
= 2 MHz
175
190
mW
TEMPERATURE RANGE
T
A
Operating free-air
40
85
C
(8)
This includes only +VA current. +VBD current is typically 1 mA with 5-pF load capacitance on output pins.
4
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TIMING CHARACTERISTICS
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
All specifications typical at 40
C to 85
C, +VA = +VBD = 5 V
(1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
t
CONV
Conversion time
340
400
ns
t
ACQ
Acquisition time
100
ns
t
pd1
CONVST low to BUSY high
30
ns
t
pd2
Propagation delay time, end of conversion to BUSY low
5
ns
t
w1
Pulse duration, CONVST low
20
ns
t
su1
Setup time, CS low to CONVST low
0
ns
t
w2
Pulse duration, CONVST high
20
ns
CONVST falling edge jitter
10
ps
t
w3
Pulse duration, BUSY signal low
Min(t
ACQ
)
ns
t
w4
Pulse duration, BUSY signal high
370
ns
Hold time, first data bus data transition (RD low, or CS low for read
t
h1
40
ns
cycle, or BYTE input changes) after CONVST low
t
d1
Delay time, CS low to RD low (or BUSY low to RD low)
0
ns
t
su2
Setup time, RD high to CS high
0
ns
t
w5
Pulse duration, RD low
50
ns
t
en
Enable time, RD low (or CS low for read cycle) to data valid
20
ns
t
d2
Delay time, data hold from RD high
0
ns
t
d3
Delay time, BYTE rising edge or falling edge to data valid
2
20
ns
t
w6
Pulse duration, RD high
20
ns
t
w7
Pulse duration, CS high
20
ns
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
t
h2
50
ns
falling edge
t
su3
Setup time, BYTE transition to RD falling edge
0
ns
t
h3
Hold time, BYTE transition to RD falling edge
0
ns
t
dis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
20
ns
t
d5
Delay time, end of conversion to MSB data valid
10
ns
Byte transition setup time, from BYTE transition to next BYTE
t
su4
50
ns
transition
t
d6
Delay time, CS rising edge to BUSY falling edge
50
ns
t
d7
Delay time, BUSY falling edge to CS rising edge
50
ns
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
t
su(AB)
60
340
ns
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
t
su5
MAX(t
CONV
) + MAX(t
d5
)
ns
current conversion
Hold time, data (MSB) from previous conversion hold valid from
t
h4
MIN(t
CONV
)
ns
falling edge of CONVST
(1)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See timing diagrams.
(3)
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
5
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TIMING CHARACTERISTICS
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
All specifications typical at 40
C to 85
C, +VA = 5 V, +VBD = 3 V
(1) (2) (3)
PARAMETER
MIN
TYP
MAX
UNIT
t
CONV
Conversion time
340
400
ns
t
ACQ
Acquisition time
100
ns
t
pd1
CONVST low to conversion started (BUSY high)
40
ns
t
pd2
Propagation delay time, end of conversion to BUSY low
10
ns
t
w1
Pulse duration, CONVST low
20
ns
t
su1
Setup time, CS low to CONVST low
0
ns
t
w2
Pulse duration, CONVST high
20
ns
CONVST falling edge jitter
10
ps
t
w3
Pulse duration, BUSY signal low
Min(t
ACQ
)
ns
t
w4
Pulse duration, BUSY signal high
370
ns
Hold time, first data bus transition (RD low, or CS low for read cycle,
t
h1
40
ns
or BYTE input changes) after CONVST low
t
d1
Delay time, CS low to RD low (or BUSY low to RD low)
0
ns
t
su2
Setup time, RD high to CS high
0
ns
t
w5
Pulse duration, RD low
50
ns
t
en
Enable time, RD low (or CS low for read cycle) to data valid
30
ns
t
d2
Delay time, data hold from RD high
0
ns
t
d3
Delay time, BYTE rising edge or falling edge to data valid
2
30
ns
t
w6
Pulse duration, RD high
20
ns
t
w7
Pulse duration, CS high
20
ns
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
t
h2
50
ns
falling edge
t
su3
Setup time, BYTE transition to RD falling edge
0
ns
t
h3
Hold time, BYTE transition to RD falling edge
0
ns
t
dis
Disable time, RD high (CS high for read cycle) to 3-stated data bus
30
ns
t
d5
Delay time, end of conversion to MSB data valid
20
ns
Byte transition setup time, from BYTE transition to next BYTE
t
su4
50
ns
transition
t
d6
Delay time, CS rising edge to BUSY falling edge
50
ns
t
d7
Delay time, BUSY falling edge to CS rising edge
50
ns
Setup time, from the falling edge of CONVST (used to start the valid
conversion) to the next falling edge of CONVST (when CS = 0 and
t
su(AB)
70
350
ns
CONVST used to abort) or to the next falling edge of CS (when CS is
used to abort)
Setup time, falling edge of CONVST to read valid data (MSB) from
t
su5
MAX(t
CONV
) + MAX(t
d5
)
ns
current conversion
Hold time, data (MSB) from previous conversion hold valid from
t
h4
MIN(t
CONV
)
ns
falling edge of CONVST
(1)
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2)
See timing diagrams.
(3)
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.
6
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PIN ASSIGNMENTS
11
NC - No connection
+VBD
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
1 2
37
38
39
40
41
42
43
44
45
46
47
48
+VBD
RESET
BYTE
CONVST
RD
CS
+VA
AGND
AGND
+VA
REFM
REFM
3
4 5
6
PFB PACKAGE
(TOP VIEW)
DB4
DB5
DB6
DB7
35 34 33 32 31
36
30
BUSY
BDGND
+VBD
DB0
DB1
DB2
DB3
AGND
+V
A
+V
A
REFIN
REFOUT
NC
+V
A
AGND
+IN
-IN
28 27 26
29
7 8
9 10
AGND
24
23
22
21
20
19
18
17
16
15
14
13
AGND
12
BDGND
25
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
7
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ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
Terminal Functions
NAME
NO.
I/O
DESCRIPTION
AGND
5, 8, 11, 12, 14,
Analog ground
15, 44, 45
BDGND
25, 35
Digital ground for bus interface digital supply
BUSY
36
O
Status output. High when a conversion is in progress.
BYTE
39
I
Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most
significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
CONVST
40
I
Convert start. The falling edge of this input ends the acquisition period and starts the hold
period.
CS
42
I
Chip select. The falling edge of this input starts the acquisition period.
8-Bit Bus
16-Bit Bus
Data Bus
BYTE = 0
BYTE = 1
BYTE = 0
DB15
16
O
D15 (MSB)
D7
D15 (MSB)
DB14
17
O
D14
D6
D14
DB13
18
O
D13
D5
D13
DB12
19
O
D12
D4
D12
DB11
20
O
D11
D3
D11
DB10
21
O
D10
D2
D10
DB9
22
O
D9
D1
D9
DB8
23
O
D8
D0 (LSB)
D8
DB7
26
O
D7
All ones
D7
DB6
27
O
D6
All ones
D6
DB5
28
O
D5
All ones
D5
DB4
29
O
D4
All ones
D4
DB3
30
O
D3
All ones
D3
DB2
31
O
D2
All ones
D2
DB1
32
O
D1
All ones
D1
DB0
33
O
D0 (LSB)
All ones
D0 (LSB)
IN
7
I
Inverting input channel
+IN
6
I
Non inverting input channel
NC
3
No connection
REFIN
1
I
Reference input
REFM
47, 48
I
Reference ground
REFOUT
2
O
Reference output. Add 1 F capacitor between the REFOUT pin and REFM pin when internal
reference is used.
RESET
38
I
Current conversion is aborted and output latches are cleared (set to zeros) when this pin is
asserted low. RESET works independantly of CS.
RD
41
I
Synchronization pulse for the parallel output. When CS is low, this serves as the output enable
and puts the previous conversion result on the bus.
+VA
4, 9, 10, 13, 43,
Analog power supplies, 5-V dc
46
+VBD
24, 34, 37
Digital power supply for bus
8
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TIMING DIAGRAMS
t
w1
CONVST
t
pd1
t
pd2
t
w4
t
su1
BUSY
CS
CONVERT
t
CONV
SAMPLING
(When CS Toggle)
BYTE
t
w2
t
w3
t
ACQ
t
h1
t
d1
t
en
RD
t
dis
t
h2
t
su2
t
CONV
Signal internal to device
D [7:0]
Hi-Z
Hi-Z
DB[15:8]
Hi-Z
Hi-Z
D [15:8]
D [7:0]
DB[7:0]
t
d6
t
su4
t
w7
t
d7
t
cycle
t
pd1
Data to
be read
Invalid
Previous Conversion
Current Conversion
Invalid
t
h4
t
su5
(used in normal
conversion)
CONVST
(used in ABORT)
t
su(AB)
t
su(AB)
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
9
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Signal internal to device
CONVST
BUSY
CS
CONVERT
SAMPLING
(When CS Toggle)
BYTE
RD = 0
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
su1
t
CONV
t
ACQ
t
CONV
t
h1
t
en
t
h2
t
dis
D [7:0]
Hi-Z
Hi-Z
DB[15:8]
Hi-Z
Hi-Z
D [15:8]
D [7:0]
DB[7:0]
t
d6
t
su4
t
w7
t
d7
D [15:8]
D [7:0]
t
dis
Hi-Z
Hi-Z
t
en
D [15:8]
D [7:0]
t
en
Previous
Previous
Repeated
Repeated
t
cycle
t
su(AB)
t
su(AB)
(used in normal
conversion)
CONVST
(used in ABORT)
Data to
be read
Invalid
Invalid
t
h4
t
su5
Previous Conversion
Current Conversion
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
10
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Signal internal to device
t
CONV
CONVST
BUSY
CS = 0
CONVERT
SAMPLING
(When CS = 0)
BYTE
RD
t
w1
t
pd2
t
pd1
t
w4
t
w2
t
w3
t
CONV
t
(ACQ)
t
h1
t
h2
t
en
t
dis
D [7:0]
Hi-Z
Hi-Z
DB[15:8]
Hi-Z
Hi-Z
D [15:8]
D [7:0]
DB[7:0]
t
su4
t
cycle
t
su(AB)
t
su(AB)
CONVST
(used in ABORT)
(used in normal
conversion)
t
pd1
Data to
be read
Invalid
Invalid
t
h4
t
su5
Previous Conversion
Current Conversion
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
11
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Signal internal to device
CONVST
BUSY
CS = 0
CONVERT
SAMPLING
(When CS Toggle)
BYTE
RD = 0
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
CONV
t
ACQ
t
CONV
Invalid
DB[15:8]
DB[7:0]
MSB
LSB
t
d3
Previous
Previous
t
cycle
t
su(AB)
t
su(AB)
(used in normal
conversion)
CONVST
(used in ABORT)
t
su5
t
pd2
t
h1
t
h1
t
pd1
t
d3
t
d3
t
h4
LSB
Previous
t
d5
Invalid
MSB
MSB
MSB
MSB
Invalid
Invalid
LSB
t
h4
t
d5
t
su5
LSB
Valid
Hi-Z
t
en
t
dis
t
en
t
d3
t
dis
Valid
Valid
Hi-Z
Hi-Z
CS
RD
BYTE
DB[15:0]
t
su4
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND--Auto Read
Figure 5. Detailed Timing for Read Cycles
12
www.ti.com
TYPICAL CHARACTERISTICS
85.2
85.4
85.6
85.8
86
86.2
86.4
86.6
86.8
-40
-20
0
20
40
60
80
SNR - Signal-to-Noise Ratio - dB
T
A
- Free-Air Temperature -
C
f
i
= 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
0
10000
20000
30000
40000
50000
60000
70000
+VA = 5 V,
+VBD = 3.3 V
Code = 65235
65230
65239
65235
13.25
13.3
13.35
13.4
13.45
13.5
13.55
13.6
-40
-20
0
20
40
60
80
ENOB - Effective Number of Bits - Bits
T
A
- Free-Air Temperature -
C
f
i
= 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
81.6
81.8
82
82.2
82.4
82.6
82.8
83
83.2
83.4
83.6
83.8
-40
-20
0
20
40
60
80
SINAD - Signal-to-Nois and Distortion - dB
T
A
- Free-Air Temperature -
C
f
i
= 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
At 40
C to 85
C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f
sample
= 2 MHz
(unless otherwise noted)
HISTOGRAM (DC CODE SPREAD)
SIGNAL-TO-NOISE RATIO
vs
vs
FULL SCALE 131071 CONVERSIONS
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
SIGNAL-TO-NOISE AND DISTORTION
EFFECTIVE NUMBER OF BITS
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 8.
Figure 9.
13
www.ti.com
92
92.5
93
93.5
94
94.5
95
95.5
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
C
f
i
= 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
SFDR - Spurious Free Dynamic Range - dB
-94.5
-94
-93.5
-93
-92.5
-92
-91.5
-91
-40
-20
0
20
40
60
80
T
A
- Free-Air Temperature -
C
THD - T
otal Harmonic Distortion - dB
f
i
= 100 kHz,
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
86
86.1
86.2
86.3
86.4
86.5
86.6
86.7
86.8
86.9
0
20
40
60
80
100
SNR - Signal-to-Noise Ratio - dB
f
i
- Input Frequency - kHz
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
13.4
13.45
13.5
13.55
13.6
13.65
13.7
13.75
13.8
13.85
13.9
0
20
40
60
80
100
ENOB - Effective Number of Bits - Bits
f
i
- Input Frequency - kHz
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
Figure 12.
Figure 13.
14
www.ti.com
94
95
96
97
98
99
100
101
102
103
0
20
40
60
80
100
f
i
- Input Frequency - kHz
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
SFDR - Spurious Free Dynamic Range - dB
82.50
83
83.50
84
84.50
85
85.50
0
20
40
60
80
100
SINAD - Signal-to-Nois and Distortion - dB
f
i
- Input Frequency - kHz
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
-101
-100
-99
-98
-97
-96
-95
-94
-93
-92
0
20
40
60
80
100
f
i
- Input Frequency - kHz
THD - T
otal Harmonic Distortion - dB
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
28.5
29
29.5
30
30.5
31
31.5
32
32.5
33
33.5
500
700
900
1100
1300
1500 1700
1900
+VA = 5 V,
+VBD = 3.3 V,
T
A
= 25
C,
Internal
Reference
I CC
- Supply Current - mA
Samply Rate - KSPS
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE AND DISTORTION
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
Figure 14.
Figure 15.
TOTAL HARMONIC DISTORTION
SUPPLY CURRENT
vs
vs
INPUT FREQUENCY
SAMPLE RATE
Figure 16.
Figure 17.
15
www.ti.com
0
0.05
0.10
0.15
0.20
0.25
4.75
4.85
4.95
5.05
5.15
5.25
V
DD
- Supply Voltage - V
- Gain Error - mV
E
G
+VBD = 3.3 V,
T
A
= 25
C,
External
Reference
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
4.75
4.85
4.95
5.05
5.15
5.25
- Offset Error - mV
E
O
V
DD
- Supply Voltage - V
+VB D= 3.3 V,
T
A
= 25
C,
External
Reference
4.083
4.084
4.085
4.086
4.087
4.088
4.089
4.090
4.091
4.092
-40
-20
0
20
40
60
80
Internal V
oltage Reference - V
+VA = 5 V,
+VBD = 3.3 V
T
A
- Free-Air Temperature -
C
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
-40
-20
0
20
40
60
80
- Gain Error - mV
E
G
+VA = 5 V,
+VBD = 3.3 V,
External
Reference
T
A
- Free-Air Temperature -
C
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
OFFSET ERROR
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 18.
Figure 19.
INTERNAL VOLTAGE REFERENCE
GAIN ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 20.
Figure 21.
16
www.ti.com
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-40
-20
0
20
40
60
80
- Offset Error - mV
E
O
+VA = 5 V,
+VBD = 3.3 V,
External
Reference
T
A
- Free-Air Temperature -
C
32
32.2
32.4
32.6
32.8
33
33.2
33.4
33.6
-40
-20
0
20
40
60
80
+VA = 5 V,
+VBD = 3.3 V
T
A
- Free-Air Temperature -
C
I CC
- Supply Current - mA
-1.5
-1
-0.5
0
0.5
1
1.5
2
-40
-20
0
20
40
60
80
Max
Min
+VA = 5 V,
+VBD = 3.3 V,
Internal
Reference
T
A
- Free-Air Temperature -
C
DNL
- Differential Nonlinearity - LSBs
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
-40
-25
-10
5
20
35
50
65
80
T
A
- Free-Air Temperature -
C
INL
- Integral Nonlinearity - LSBs
MAX
MIN
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 22.
Figure 23.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 24.
Figure 25.
17
www.ti.com
-4
-3
-2
-1
0
1
2
3
4
0
32768
65536
DNL
- LSBs
Code
16384
49152
-4
-3
-2
-1
0
1
2
3
4
0
16384
65536
INL
- LSBs
Code
32768
49152
-160
-180
0
100
200
300
400
500
600
-100
-60
0
700
800
900
-140
-120
-80
-40
-20
Magnitude - dB
Frequency - kHz
1000
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
DNL
Figure 26.
INL
Figure 27.
FFT
Figure 28.
18
www.ti.com
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8411 to 8-Bit Microcontroller Interface
CS
RD
CONVST
BUSY
BDGND
+VBD
DB[15:8]
Micro
Controller
RD
GPIO
INT
10
F
0.1
F
Analog 5 V
0.1
F
Digital 3 V
Ext Ref Input
Analog Input
+V
A
REFM
AGND
+IN
-IN
ADS8411
0.1
F
REFIN
1
F
AGND
BDGND
GPIO
BYTE
P[7:0]
GPIO
+V
A
REFOUT
REFIN
REFM
AGND
0.1
F
1
F
0.1
F
10
F
Analog 5 V
ADS8411
AGND
AGND
PRINCIPLES OF OPERATION
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
Figure 29 shows a parallel interface between the ADS8411 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Figure 29. ADS8411 Application Circuitry (using external reference)
Figure 30. Use Internal Reference
The ADS8411 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 29
for the application circuit for the ADS8411.
The conversion clock is generated internally. The conversion time of 400 ns is capable of sustaining a 2-MHz
throughput.
19
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REFERENCE
ANALOG INPUT
DIGITAL INTERFACE
Timing And Control
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins: +IN and IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The ADS8411 can operate with an external reference with a range from 3.9 V to 4.2 V. A 4.096-V internal
reference is included. When the internal reference is used, pin 2 (REFOUT) should be connected to pin 1
(REFIN) with 0.1-F decoupling capacitor and 1-F storage capacitor between pin 2 (REFOUT) and pins 47 and
48 (REFM) (see Figure 30). The internal reference of the converter is double buffered. If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also
used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected
(floating) if an external reference is used.
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on
the internal capacitor array. The voltage on the IN input is limited between 0.2 V and 0.2 V, allowing the input
to reject small signals which are common to both the +IN and IN inputs. The +IN input has a range of 0.2 V to
V
ref
+ 0.2 V. The input span (+IN (IN)) is limited to 0 V to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8411 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (100 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
G
.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and IN inputs and the span (+IN (IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and IN inputs are
matched. If this is not observed, the two inputs could have different setting time. This may result in offset error,
gain error and linearity error which varies with temperature and input voltage.
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8411 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8411 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
20
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Reading Data
RESET
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The ADS8411 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.
This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be
attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used
for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher
byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT
Full scale range
V
ref
STRAIGHT BINARY
Least significant bit (LSB)
V
ref
/65536
BINARY CODE
HEX CODE
Full scale
V
ref
1 LSB
1111 1111 1111 1111
FFFF
Midscale
V
ref
/2
1000 0000 0000 0000
8000
Midscale 1 LSB
V
ref
/2 1 LSB
0111 1111 1111 1111
7FFF
Zero
0 V
0000 0000 0000 0000
0000
The output data is a full 16-bit word (D15D0) on DB15DB0 pins (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7D0) appear on pins DB15D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
DATA READ OUT
BYTE
DB15DB8 Pins
DB7-DB0 Pins
High
D7D0
All one's
Low
D15D8
D7-D0
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure a reset.The falling edge of
CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the
falling edge is replaced by the falling edge of CS.
21
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POWER-ON INITIALIZATION
LAYOUT
ADS8411
SLAS369B APRIL 2002 REVISED DECEMBER 2004
RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all
of the registers are cleared, the three conversion cycles must be given to the converter after power on.
For optimum performance, care should be taken with the physical layout of the ADS8411 circuitry.
As the ADS8411 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8411 draws very little current from an external reference, as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-F bypass capacitor and a 1-F storage capacitor
are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the
same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8411
should be clean and well bypassed. A 0.1-F ceramic bypass capacitor should be placed as close to the device
as possible. See Table 3 for the placement of the capacitor. In addition, a 1-F to 10-F capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-F electrolytic capacitor
or even a Pi filter made up of inductors and capacitors--all designed to essentially low-pass filter the 5-V supply,
removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
SUPPLY PINS
(4,5), (8,9), (10,11), (13,15),
Pin pairs that require shortest path to decoupling capacitors
(24,25), (34, 35)
(43,44), (45,46)
Pins that require no decoupling
12, 14
37
22
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