AFE1103

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1996 Burr-Brown Corporation

PDS-1330A

Printed in U.S.A. August, 1996

HDSL/MDSL ANALOG FRONT END

FEATURES

COMPLETE ANALOG INTERFACE

T1, E1, AND MDSL OPERATION

CLOCK SCALEABLE SPEED

SINGLE CHIP SOLUTION

+5V ONLY (5V OR 3.3V DIGITAL)

250mW POWER DISSIPATION

48-PIN SSOP

40

C TO +85

C OPERATION

SECOND SOURCED BY BROOKTREE
Bt8921

DESCRIPTION

Burr-Brown's Analog Front End greatly reduces the
size and cost of an HDSL or MDSL system by provid-
ing all of the active analog circuitry needed to connect
the Brooktree Bt8952 HDSL digital signal processor
to an external compromise hybrid and a 1:2 HDSL line
transformer. All internal filter responses as well as the
pulse former output scale with clock frequency--
allowing the AFE1103 to operate over a range of bit
rates from 196kbps to 1.168Mbps.

Functionally, this unit is separated into a transmit and
a receive section. The transmit section generates, fil-
ters, and buffers outgoing 2B1Q data. The receive
section filters and digitizes the symbol data received
on the telephone line and passes it to the Bt8952. The
HDSL Analog Interface is a monolithic device fabri-
cated on 0.6

CMOS. It operates on a single +5V

supply. It is housed in a 48-pin SSOP package. This
unit is second sourced by Brooktree's Bt8921.

Pulse

Former

PLL

OUT

PLL

txDAT

txCLK

rxSYNC

rxLOOP

rxGAIN

rxD13 - rxD0

Line

Driver

Voltage

Reference

Delta-Sigma

Modulator

Transmit

Control

Receive

Control

Decimation

Filter

txLINE

REF

rxLINE

rxHYB

Patents Pending

AFE1103

SPECIFICATIONS

Typical at 25

C, AV

= +5V, DV

= +3.3V, f

= 584kHz (E1 rate), unless otherwise specified.

AFE1103E

PARAMETER

COMMENTS

MIN

TYP

MAX

UNITS

RECEIVE CHANNEL
Number of Inputs

Differential

Input Voltage Range

Balanced Differential

(1)

3.0

Common-Mode Voltage

1.5V CMV Recommended

+1.5

Input Impedance

All Inputs

See Typical Performance Curves

Input Capacitance

Input Gain Matching

Line Input vs Hybrid Input

Resolution

Bits

Programmable Gain

Four Gains: 0dB, 3.25dB, 6dB, and 9dB

Settling Time for Gain Change

Symbol
Periods

Gain + Offset Error

Tested at Each Gain Range

%FSR

(2)

Output Data Coding

Offset Binary

Output Data Rate, rxSYNC

(3)

584

kHz

TRANSMIT CHANNEL
Transmit Symbol Rate, f

584

kHz

T1 Transmit 3dB Point

Bellcore TA-NWT-3017 Compliant

196

kHz

T1 Rate Power Spectral Density

(4)

See Typical Performance Curves

E1 Transmit 3dB Point

ETSI RTR/TM-03036 Compliant

292

kHz

E1 Rate Power Spectral Density

(4)

See Typical Performance Curves

Transmit Power

(4, 5)

dBm

Pulse Output

See Typical Performance Curves

Common-Mode Voltage, V

Output Resistance

(6)

DC to 1MHz

TRANSCEIVER PERFORMANCE
Uncancelled Echo

(7)

rxGAIN = 0dB, Loopback Enabled

rxGAIN = 0dB, Loopback Disabled

rxGAIN = 3.25dB, Loopback Disabled

rxGAIN = 6dB, Loopback Disabled

rxGAIN = 9dB, Loopback Disabled

DIGITAL INTERFACE

(6)

Logic Levels

| < 10

+0.3

| < 10

0.3

+0.8

= 20

0.5

= 20

+0.4

Transmit/Receive Channel Interface

tx1

txCLK Period

1.7

10.2

tx2

txCLK Pulse Width

tx1

/16

15t

tx1

/16

POWER
Analog Power Supply Voltage

Specification

Analog Power Supply Voltage

Operating Range

4.75

5.25

Digital Power Supply Voltage

Specification

3.3

Digital Power Supply Voltage

Operating Range

3.15

5.25

Power Dissipation

(4, 5, 8)

= 3.3V

250

Power Dissipation

(4, 5, 8)

= 5V

300

PSRR

TEMPERATURE RANGE
Operating

(6)

+85

NOTES: (1) With a balanced differential signal, the positive input is 180

out of phase with the negative input, therefore the actual voltage swing about the common

mode voltage on each pin is

1.5V to achieve a differential input range of

3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the

symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from
txLINE

and txLINE

). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization. (7)

Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion
of Specifications section of this data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include
power dissipated in the external loads. See the Discussion of Specifications section for more information.

AFE1103

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PIN DESCRIPTIONS

PIN #

TYPE

NAME

DESCRIPTION

Ground

PGND

Analog Ground for PLL

Power

Analog Supply (+5V) for PLL

Input

txCLK

Symbol Clock (QCLK from Bt8952) (392kHz for T1, 584kHz for E1)

Input

txDAT

XMITB Line from Bt8952

Input

txDAT

XMIT Line from Bt8952

Output

rxD0

ADC Output Bit-0 (RCV 2 from Bt8952)

Output

rxD1

ADC Output Bit-1 (RCV 3 from Bt8952)

Output

rxD2

ADC Output Bit-2 (RCV 4 from Bt8952)

Output

rxD3

ADC Output Bit-3 (RCV 5 from Bt8952)

Output

rxD4

ADC Output Bit-4 (RCV 6 from Bt8952)

Output

rxD5

ADC Output Bit-5 (RCV 7 from Bt8952)

Ground

DGND

Digital Ground

Power

Digital Supply (+3.3V to +5V)

Output

rxD6

ADC Output Bit-6 (RCV 8 from Bt8952)

Output

rxD7

ADC Output Bit-7 (RCV 9 from Bt8952)

Output

rxD8

ADC Output Bit-8 (RCV 10 from Bt8952)

Output

rxD9

ADC Output Bit-9 (RCV 11 from Bt8952)

Output

rxD10

ADC Output Bit-10 (RCV 12 from Bt8952)

Output

rxD11

ADC Output Bit-11 (RCV 13 from Bt8952)

Output

rxD12

ADC Output Bit-12 (RCV 14 from Bt8952)

Output

rxD13

ADC Output Bit-13 (RCV 15 from Bt8952)

Ground

DGND

Digital Ground

Input

rxSYNC

ADC Sync Signal (RCVCLK from Bt8952) (392kHz for T1, 584kHz for E1)

Input

rxGAIN0

Receive Gain Control Bit-0

Input

rxGAIN1

Receive Gain Control Bit-1

Input

rxLOOP

Loopback Control Signal (loopback is enabled by positive signal)

Power

Analog Supply (+5V)

Input

rxHYB

Negative Input from Hybrid Network

Input

rxHYB

Positive Input from Hybrid Network

Input

rxLINE

Negative Line Input

Input

rxLINE

Positive Line Input

Ground

AGND

Analog Ground

Ground

AGND

Analog Ground

Output

REF

Positive Reference Output, Nominally 3.5V

Output

Common-Mode Voltage (buffered), Nominally 2.5V

Output

REF

Negative Reference Output, Nominally 1.5V

Power

Analog Supply (+5V)

Ground

AGND

Analog Ground

Output

txLINE

Transmit Line Output Negative

Power

Analog Supply (+5V)

Output

txLINE

Transmit Line Output Positive

Ground

AGND

Analog Ground

Connection to Ground Recommended

Output

PLL

OUT

PLL Filter Output

Input

PLL

PLL Filter Input

AFE1103

PIN CONFIGURATION

Top View

SSOP

PGND

txCLK

txDAT

rxD0

rxD1

rxD2

rxD3

rxD4

rxD5

DGND

rxD6

rxD7

rxD8

rxD9

rxD10

rxD11

rxD12

rxD13

DGND

rxSYNC

rxGAIN0

PLL

OUT

AGND

txLINE

AGND

REF

AGND

rxLINE

rxHYB

rxLOOP

rxGAIN1

AFE1103E

Analog Inputs: Current ..............................................

100mA, Momentary

10mA, Continuous

Voltage .................................. AGND 0.3V to AV

+0.3V

Analog Outputs Short Circuit to Ground (+25

C) ..................... Continuous

to AGND ........................................................................ 0.3V to 6V

to PGND ........................................................................ 0.3V to 6V

to DGND ........................................................................ 0.3V to 6V

PLL

or PLL

OUT

to PGND ......................................... 0.3V to PV

+0.3V

Digital Input Voltage to DGND .................................. 0.3V to DV

+0.3V

Digital Output Voltage to DGND ............................... 0.3V to DV

+0.3V

AGND, DGND, PGND Differential Voltage ......................................... 0.3V
Junction Temperature (T

) ............................................................ +150

Storage Temperature Range .......................................... 40

C to +125

Lead Temperature (soldering, 3s) ................................................. +260

Power Dissipation ......................................................................... 700mW

ABSOLUTE MAXIMUM RATINGS

PACKAGE

DRAWING

TEMPERATURE

PRODUCT

PACKAGE

NUMBER

(1)

RANGE

AFE1103E

48-Pin Plastic SSOP

333

C to +85

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

AFE1103

TYPICAL PERFORMANCE CURVES

At Output of Pulse Transformer

Typical at 25

C, AV

= +5V, DV

= +3.3V, unless otherwise specified.

CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output.

CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output.

0.4T

B = 1.07

C = 1.00
D = 0.93

0.4T

0.6T

1.2T

A = 0.01

E = 0.03

G = 0.16

A
B
C
D
E
F

G
H

0.01
1.07
1.00
0.93
0.03

0.01
0.16
0.05

0.0264
2.8248
2.6400
2.4552
0.0792

0.0264
0.4224
0.1320

0.0264
2.8248
2.6400
2.4552
0.0792

0.0264
0.4224
0.1320

0.0088
0.9416
0.8800
0.8184
0.0264

0.0088
0.1408
0.0440

0.0088
0.9416
0.8800
0.8184
0.0264

0.0088
0.1408
0.0440

NORMALIZED

LEVEL

QUATERNARY SYMBOLS

14T

H = 0.05

50T

F = 0.01

A = 0.01

F = 0.01

0.5T

1.25T

CURVE 3. Input Impedance of rxLINE and rxHYB.

100

120

10K

100K

POWER SPECTRAL DENSITY LIMIT

Power Spectral Density (dBm/Hz)

Frequency (Hz)

10M

38dBm/Hz for T1

40dBm/Hz for E1

196kHz

292kHz

80dB/decade

120dBm/Hz

for E1

118dBm/Hz

100

200

150

100

300

500

INPUT IMPEDANCE vs BIT RATE

Input Impedance (k

)

Bit Rate (kbps)

700

900

1300

1100

T1 = 784kbps, 45k

E1 = 1168kbps, 30k

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