1998 Burr-Brown Corporation

PDS-1460A

Printed in U.S.A. October, 1998

2Mbps, Single Pair HDSL ANALOG FRONT END

FEATURES

E1/T1 SINGLE PAIR 2B1Q OPERATION

COMPLETE ANALOG INTERFACE

385mW POWER DISSIPATION

PROGRAMMABLE POWER

AFE1203

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DESCRIPTION

Burr-Brown's Analog Front End greatly reduces the size and
cost of a single pair HDSL (High bit rate Digital Subscriber
Line) system by providing all of the active analog circuitry
needed to connect an HDSL digital signal processor to an
external compromise hybrid and an HDSL line transformer.
The transmit and receive filter responses automatically change
with clock frequency, allowing the AFE1203 to operate over a
wide range of data rates. The power dissipation of the device
can be reduced under digital control for operation at lower
speeds. The AFE1203 will operate at bit rates from 160kbps to
2.3Mbps. It meets ETSI PSD specifications for single pair E1,
as well as ETSI and ANSI PSD specifications for two pair E1
and T1.

Functionally, this unit consists of a transmit and a receive
section. The transmit section generates, filters, and buffers
outgoing 2B1Q data. The receive section filters and digitizes
the symbol data received on the telephone line. This IC operates

48-LEAD SSOP PACKAGE

SCALEABLE DATA RATE

OPERATION FROM 2.3Mbps TO 160kbps

+5V ONLY (5V OR 3.3V DIGITAL)

40

C TO +85

C OPERATION

on a single 5V supply. The digital circuitry in the unit can be
connected to a supply from 3.3V to 5V. The chip uses only
385mW for full-speed operation. It is housed in a small 48-lead
SSOP package.

The receive channel is designed around a fourth-order delta-
sigma analog-to-digital converter. It includes a difference am-
plifier designed to be used with an external compromise hybrid
for first-order analog echo cancellation. A programmable gain
amplifier with gains 0dB to +9dB is also included. The delta-
sigma modulator, operating at a 24X oversampling ratio, pro-
duces a 14-bit output at symbol rates up to 1168kHz (for
2.3Mbps operation).

The transmit channel consists of a digital-to-analog converter and
switched-capacitor pulse forming network followed by a differ-
ential line driver. The pulse forming network receives symbol
data and generates a standard 2B1Q output waveform. The
differential line driver uses a composite output stage combining
class B operation (for high efficiency driving large signals) with
class AB operation (to minimize crossover distortion).

Pulse

Former

PLL

OUT

PLL

txDAT

txCLK

rxSYNC

rxLOOP

rxGAIN

rxD13 - rxD0

Line

Driver

Voltage

Reference

Delta-Sigma

Modulator

Transmit

Control

Receive

Control

Decimation

Filter

txLINE

REF

rxLINE

rxHYB

Patents Pending

D/A

Converter

AFE1203

AFE1203

SPECIFICATIONS

Typical at 25

C, AV

= +5V, DV

= +3.3V, f

= 1168kHz (E1 single pair rate) and Normal Power mode, unless otherwise specified.

AFE1203E

PARAMETER

COMMENTS

MIN

TYP

MAX

UNITS

RECEIVE CHANNEL
Number of Inputs

Differential

Input Voltage Range

Balanced Differential

(1)

3.0

Common-Mode Voltage

1.5V CMV Recommended

+1.5

Input Impedance

All Inputs

See Typical Performance Curves

Input Capacitance

Input Gain Matching

Line Input vs Hybrid Input

Resolution

Bits

Programmable Gain

Four Gains: 0dB, 3.25dB, 6dB, and 9dB

Settling Time

Gain, rxSYNC, or Power Mode Change

(8)

Symbol
Periods

Gain + Offset Error

Tested at Each Gain Range

%FSR

(2)

Output Data Coding

Binary Two's Complement

Data Rate

Normal Power

384

2320

kbps

Medium Power

192

1168

kbps

Low Power

160

320

kbps

Output Word Rate

Normal Power, rxSYNC

(3)

196

1168

kHz

TRANSMIT CHANNEL
Transmit Clock Rate, f

Symbol Rate, Normal Power

196

1168

kHz

Symbol Rate, Medium Power

584

kHz

Symbol Rate, Low Power

160

kHz

Transmit 3dB Point

2320kbps

485

kHz

1168kbps

292

kHz

784kbps

196

kHz

Transmit Power

(4)

13.5

dBm

Pulse Output

See Typical Performance Curves

Common-Mode Voltage, V

Output Resistance

(5)

DC to 1MHz

TRANSCEIVER PERFORMANCE
Uncancelled Echo

(6)

rxGAIN = 0dB, Loopback Enabled

rxGAIN = 0dB, Loopback Disabled

rxGAIN = 3.25dB, Loopback Disabled

rxGAIN = 6dB, Loopback Disabled

rxGAIN = 9dB, Loopback Disabled

DIGITAL INTERFACE

(5)

Logic Levels

| < 10

+ 0.3

| < 10

0.3

+0.8

= 20

0.5

= 20

+0.4

POWER
Analog Power Supply Voltage

Specification

Operating Range

4.75

5.25

Digital Power Supply Voltage

Specification

3.3

Operating Range

3.15

5.25

Power Dissipation

(4, 7)

Normal Power

385

Medium Power

300

Low Power

240

Power Dissipation

(7)

Normal Power, DV

= 5V

415

PSRR

TEMPERATURE RANGE
Operating

(5)

+85

NOTES: (1) With a balanced differential signal, the positive input is 180

out of phase with the negative input, therefore the actual voltage swing about the common

mode voltage on each pin is

1.5V to achieve a differential input range of

3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the

symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from
txLINE

and txLINE

). (5) Guaranteed by design and characterization. (6) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver

sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (7) Power dissipation
includes only the power dissipated within the component and does not include power dissipated in the external loads. The AFE1203 is tested with a 1:2 line
transformer. (8) This is the settling time required for any gain change, change of rxSYNC or any change of power mode.

AFE1203

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PIN DESCRIPTIONS

PIN #

TYPE

NAME

DESCRIPTION

Ground

AGND

Analog Ground for PLL

Power

Analog Supply (+5V) for PLL

Input

txCLK

Symbol Clock

Input

txDAT

XMITB Line

Input

txDAT

XMIT Line

Output

rxD0

ADC Output Bit-0

Output

rxD1

ADC Output Bit-1

Output

rxD2

ADC Output Bit-2

Output

rxD3

ADC Output Bit-3

Output

rxD4

ADC Output Bit-4

Output

rxD5

ADC Output Bit-5

Ground

DGND

Digital Ground

Power

Digital Supply (+3.3V to +5V)

Output

rxD6

ADC Output Bit-6

Output

rxD7

ADC Output Bit-7

Output

rxD8

ADC Output Bit-8

Output

rxD9

ADC Output Bit-9

Output

rxD10

ADC Output Bit-10

Output

rxD11

ADC Output Bit-11

Output

rxD12

ADC Output Bit-12

Output

rxD13

ADC Output Bit-13

Input

PWSEL

Power Control

Input

rxSYNC

ADC Sync Signal

Input

rxGAIN0

Receive Gain Control Bit-0

Input

rxGAIN1

Receive Gain Control Bit-1

Input

rxLOOP

Loopback Control Signal (loopback is enabled by positive signal)

Power

Analog Supply (+5V)

Input

rxHYB

Negative Input from Hybrid Network

Input

rxHYB

Positive Input from Hybrid Network

Input

rxLINE

Negative Line Input

Input

rxLINE

Positive Line Input

Ground

AGND

Analog Ground

Ground

AGND

Analog Ground

Output

REF

Positive Reference Output, Nominally 3.5V

Output

Common-Mode Voltage (buffered), Nominally 2.5V

Output

REF

Negative Reference Output, Nominally 1.5V

Power

Analog Supply (+5V)

Ground

AGND

Analog Ground

Output

txLINE

Transmit Line Output Negative

Power

Analog Supply (+5V)

Output

txLINE

Transmit Line Output Positive

Ground

AGND

Analog Ground

Connection to Ground Recommended

Output

PLL

OUT

PLL Filter Output

Input

PLL

PLL Filter Input

AFE1203

PIN CONFIGURATION

Top View

SSOP

Analog Inputs: Current ..............................................

100mA, Momentary

10mA, Continuous

Voltage .................................. AGND 0.3V to AV

+ 0.3V

Analog Outputs Short Circuit to Ground (+25

C) ..................... Continuous

to AGND ......................................................................... 0.3V to 6V

to DGND ......................................................................... 0.3V to 6V

PLL

or PLL

OUT

to AGND ........................................ 0.3V to AV

+ 0.3V

Digital Input Voltage to DGND ................................. 0.3V to DV

+ 0.3V

Digital Output Voltage to DGND .............................. 0.3V to DV

+ 0.3V

AGND, DGND Differential Voltage ..................................................... 0.3V
Junction Temperature (T

) ............................................................ +150

Storage Temperature Range .......................................... 40

C to +125

Lead Temperature (soldering, 3s) ................................................. +260

Power Dissipation ......................................................................... 700mW

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PACKAGE

DRAWING

TEMPERATURE

PRODUCT

PACKAGE

NUMBER

(1)

RANGE

AFE1203E

48-Lead SSOP

333

C to +85

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

AGND

txCLK

txDAT

rxD0

rxD1

rxD2

rxD3

rxD4

rxD5

DGND

rxD6

rxD7

rxD8

rxD9

rxD10

rxD11

rxD12

rxD13

PWSEL

rxSYNC

rxGAIN0

PLL

OUT

AGND

txLINE

AGND

REF

AGND

rxLINE

rxHYB

rxLOOP

rxGAIN1

AFE1203E

AFE1203

TYPICAL PERFORMANCE CURVES

At Output of Pulse Transformer

Typical at 25

C, AV

= +5V, and DV

= +3.3V, unless otherwise specified.

CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output.

CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output.

CURVE 3. Input Impedance of rxLINE and rxHYB.

LOWER

BREAK

UPPER

SPEED

LIMIT

FREQUENCY

SLOPE

LIMIT

T1, Two Pair

38dBm/Hz

196kHz

80dB/decade

118dBm/Hz

E1, Two Pair

40dBm/Hz

292kHz

80dB/decade

120dBm/Hz

E1, Single Pair (E1-SP) 42.5dBm/Hz

485kHz

80dB/decade

122dBm/Hz

TWO PAIR T1 AND E1

SINGLE PAIR E1

NORMALIZED

LIMITS

LEVELS

QUATENARY SYMBOLS (V)

LEVELS

QUATENARY SYMBOLS (V)

0.01

0.0264

0.0088

0.0088 0.0264

0.01

0.0250

0.0083

0.0250

1.07

2.8248

0.9416

0.9416 2.8248

1.07

2.6750

0.8917

0.8917 2.6750

1.00

2.6400

0.8800

0.8800 2.6400

1.00

2.5000

0.8333

0.8333 2.5000

0.93

2.4552

0.8184

0.8184 2.4552

0.93

2.3250

0.7750

0.7750 2.3250

0.03

0.0792

0.0264

0.0264 0.0792

0.04

0.1000

0.0333

0.0333 0.1000

0.01

0.0264

0.0088

0.0264

0.01

0.0250

0.0083

0.0250

0.16

0.4224

0.1408

0.4224

0.20

0.5000

0.1667

0.5000

0.05

0.1320

0.0440

0.1320

0.05

1.2500

0.0417

0.1250

0.4T 0.4T

0.6T

1.2T

14T

50T

0.5T

1.25T

200

100

600

1000

INPUT IMPEDANCE vs BIT RATE

Input Impedance (k

)

Bit Rate (kbps)

1400

1800

2600

2200

Two Pair T1 = 784kbps, 45k

Two Pair E1 = 1168kbps, 30k

Single Pair E1 = 2320kbps, 15k

E1,

Single Pair

100

120

140

10k

100k

100M

AVERAGE POWER SPECTRAL DENSITY LIMIT

Power Spectral Density (dBm/Hz)

Frequency (Hz)

10M

E1-SP

80dB/decade

E1-SP

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