DAC1220

20-Bit Low Power

DIGITAL-TO-ANALOG CONVERTER

FEATURES

20-BIT MONOTONICITY GUARANTEED

OVER 40

C to +85

LOW POWER: 2.5mW

VOLTAGE OUTPUT

SETTLING TIME: 2ms to 0.012%

MAX LINEARITY ERROR:

0.0015%

ON-CHIP CALIBRATION

APPLICATIONS

PROCESS CONTROL

ATE PIN ELECTRONICS

CLOSED-LOOP SERVO-CONTROL

SMART TRANSMITTERS

PORTABLE INSTRUMENTS

DESCRIPTION

The DAC1220 is a 20-bit digital-to-analog (D/A)
converter offering 20-bit monotonic performance over
the specified temperature range. It utilizes delta-sigma
technology to achieve inherently linear performance
in a small package at very-low power. The resolution
of the device can be programmed to 20 bits for full-
scale, settling to 0.003% within 15ms typical, or 16
bits for full-scale, settling to 0.012% within 2ms max.
The output range is two times the external reference
voltage. On-chip calibration circuitry dramatically re-
duces low offset and gain errors.

The DAC1220 features a synchronous serial interface.
In single-converter applications, the serial interface
can be accomplished with just two wires, allowing
low-cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.

The DAC1220 has been designed for closed-loop
control applications in the industrial process control
market and high-resolution applications in the test and
measurement market. It is also ideal for remote appli-
cations, battery-powered instruments, and isolated sys-
tems. The DAC1220 is available in a SSOP-16
package.

PDS-1418B

Printed in U.S.A. April , 2000

International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111

Twx: 910-952-1111 · Internet: http://www.burr-brown.com/ · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

Clock Generator

Serial

Interface

Second-Order

Modulator

Instruction Register
Command Register

Data Register

Offset Register

Full-Scale Register

Microcontroller

First-Order

Switched

Capacitor Filter

Second-Order

Continuous

Time Post Filter

Modulator Control

AGND

OUT

REF

DGND

SDIO

OUT

SCLK

DAC1220

For most current data sheet and other product

information, visit www.burr-brown.com

DAC1220

SPECIFICATIONS

All specifications T

MIN

to T

MAX

, AV

= DV

= +5V, f

XIN

= 2.5MHz, V

REF

= +2.5V, and 16-bit mode, unless otherwise noted.

DAC1220E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Monotonicity

Bits

Monotonicity

20-Bit Mode

Bits

Linearity Error

(1)

LSB

Unipolar Offset Error

(2)

OUT

= 20mV

LSB

Unipolar Offset Error Drift

(3)

ppm/

Bipolar Zero Offset Error

(2)

OUT

= V

REF

LSB

Bipolar Zero Offset Drift

(3)

ppm/

Gain Error

(2)

LSB

Gain Error Drift

(3)

ppm/

Power Supply Rejection Ratio

at DC, dB = 20log(

OUT

)

ANALOG OUTPUT

Output Voltage

(4)

2 · V

REF

Output Current

0.5

Capacitive Load

500

Short-Circuit Current

Short-Circuit Duration

GND or V

Indefinite

DYNAMIC PERFORMANCE

Settling Time

(5)

0.012%

1.8

20-Bit Mode, to

0.003%

Output Noise Voltage

0.1Hz to 10Hz

Vrms

REFERENCE INPUT

Input Voltage

2.25

2.5

2.75

Input Impedance

100

DIGITAL INPUT/OUTPUT

Logic Family

TTL-Compatible CMOS

Logic Levels (all except X

)

2.0

+0.3

0.3

0.8

= 0.8mA

3.6

= 1.6mA

0.4

Input-Leakage Current

Frequency Range (f

XIN

)

0.5

2.5

MHz

Data Format

User Programmable

Offset Two's Complement

or Straight Binary

POWER SUPPLY REQUIREMENTS

Power Supply Voltage

4.75

5.25

Supply Current

Analog Current

360

Digital Current

140

Analog Current

20-Bit Mode

460

Digital Current

20-Bit Mode

140

Power Dissipation

2.5

3.5

20-Bit Mode

3.0

Sleep Mode

0.45

TEMPERATURE RANGE

Specified Performance

+85

NOTES: (1) Valid from AGND + 20mV to AV

20mV, in the 16-bit mode. (2) Applies after calibration, in 16-bit mode. (3) Re-calibration can remove these errors.

(4) Ideal output voltage, does not take into account gain and offset error. (5) Valid from AGND +20mV to AV

20mV. Outside of this range, settling time may

be twice the value indicated. For 16-bit mode, C

= 2.2nF, C

= 0.22nF; for 20-bit mode, C

= 10nF, C

= 3.3nF.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

ABSOLUTE MAXIMUM RATINGS

(1)

to DV

...................................................................................

0.3V

to AGND ........................................................................ 0.3V to 6V

to DGND ....................................................................... 0.3V to 6V

AGND to DGND ...............................................................................

0.3V

REF

Voltage to AGND .......................................................... 2.0V to 3.0V

Digital Input Voltage to DGND .............................. 0.3V to DV

+ 0.3V

Digital Output Voltage to DGND ........................... 0.3V to DV

+ 0.3V

Package Power Dissipation ............................................. (T

JMAX

Maximum Junction Temperature (T

JMAX

) ..................................... +150

Thermal Resistance,

SSOP-16 ................................................................................ 200

C/W

Lead Temperature (soldering, 10s) ............................................... +300

NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.

PIN CONFIGURATION

Top View

SSOP

PIN DESCRIPTIONS

PIN

NAME

DESCRIPTION

Digital Supply, +5V nominal

OUT

System Clock Output (for Crystal)

System Clock Input

DGND

Digital Ground

Analog Supply, +5V nominal

DNC

Do Not Connect

DNC

Do Not Connect

DNC

Do Not Connect

Filter Capacitor, see text.

OUT

Analog Output Voltage

REF

Reference Input

AGND

Analog Ground

Chip Select Input

SDIO

Serial Data Input/Output

SCLK

Clock Input for Serial Data Transfer

PACKAGE/ORDERING INFORMATION

MAXIMUM

LINEARITY

PACKAGE

SPECIFICATION

ERROR

DRAWING

TEMPERATURE

ORDERING

TRANSPORT

PRODUCT

(LSB)

PACKAGE

NUMBER

RANGE

NUMBER

(1)

MEDIA

DAC1220E

SSOP-16

322

C to +85

DAC1220E

Rails

DAC1220E/2K5

Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "DAC1220E/2K5" will get a single 2500-piece Tape and Reel.

OUT

DGND

DNC

SCLK

SDIO

AGND

REF

OUT

DAC1220E

THEORY OF OPERATION

The DAC1220 is a precision, high dynamic range, self-
calibrating, 20-bit, delta-sigma digital-to-analog converter.
It contains a second-order delta-sigma modulator, a first-
order switched-capacitor filter, a second-order continuous-
time post filter, a microcontroller including the Instruction,
Command and Calibration registers, a serial interface, and a
clock generator circuit.

The design topology provides low system noise and good
power-supply rejection. The modulator frequency of the
delta-sigma D/A converter is controlled by the system clock.

The DAC1220 also includes complete onboard calibration
that can correct for internal offset and gain errors.
The calibration registers are fully readable and writable.
This feature allows for system calibration. The various
settings, modes, and registers of the DAC1220 are read or
written via a synchronous serial interface. This interface
operates as an externally clocked interface.

DEFINITION OF TERMS

Differential Nonlinearity Error--The differential
nonlinearity error is the difference between an actual step
width and the ideal value of 1 LSB. If the step width is
exactly 1 LSB, the differential nonlinearity error is zero.
A differential nonlinearity specification of less than 1 LSB
guarantees monotonicity.

Drift--The drift is the change in a parameter over tempera-
ture.

Full-Scale Range (FSR)--This is the magnitude of the
typical analog output voltage range which is 2 · V

REF

For example, when the converter is configured with a 2.5V
reference, the full-scale range is 5.0V.

Gain Error--This error represents the difference in the
slope between the actual and ideal transfer functions.

Linearity Error--The linearity error is the deviation of the
actual transfer function from an ideal straight line between
the data end points.

Least Significant Bit (LSB) Weight--This is the ideal
change in voltage that the analog output will change with a
change in the digital input code of 1 LSB.

Monotonicity--Monotonicity assures that the analog out-
put will increase or stay the same for increasing digital input
codes.

Offset Error--The offset error is the difference between
the expected and actual output, when the output is zero. The
value is calculated from measurements made when
V

OUT

= 20mV.

Settling Time--The settling time is the time it takes the
output to settle to its new value after the digital code has
been changed.

XIN

--The frequency of the crystal oscillator or CMOS-

compatible input signal at the X

input of the DAC1220.

ANALOG OPERATION

The system clock is divided down to provide the sample
clock for the modulator. The sample clock is used by the
modulator to convert the multi-bit digital input into a one-bit
digital output stream. The use of a 1-bit DAC provides
inherent linearity. The digital output stream is then con-
verted into an analog signal via the 1-bit DAC and then
filtered by the 1st-order switched capacitor filter.

The output of the switched-capacitor filter feeds into the
continuous time filter. The continuous time filter uses exter-
nal capacitors connected between the C

, C

, V

REF

, and

OUT

pins to adjust the settling time. The connections for the

capacitors are shown in Figure 1 (C

connects between the

REF

and C

pins, and C

connects between the V

OUT

and C

pins).

REF

OUT

DAC1220

FIGURE 1. External Capacitor Connections.

CALIBRATION

The DAC1220 offers a self-calibration mode which auto-
matically calibrates the output offset and gain. The calibra-
tion is performed once and then normal operation is re-
sumed. In general, calibration is recommended immediately
after power-on and whenever there is a "significant" change
in the operating environment. The amount of change which
should cause a re-calibration is dependent on the applica-
tion. Where high accuracy is important, re-calibration should
be done on changes in temperature and power supply.

After a calibration has been accomplished, the Offset Cali-
bration Register (OCR) and the Full-Scale Calibration Reg-
ister (FCR) contain the results of the calibration.

Note that the values in the calibration registers will vary
from configuration-to-configuration and from part to part.

CAPACITOR

16-BIT MODE

20-BIT MODE

2.2nF

10nF

0.22nF

3.3nF

TABLE I. External Capacitor Values.

DAC1220

Self-Calibration

A self-calibration is performed after the bits "01" have been
written to the Command Register Operation Mode bits
(MD1 through MD0) and a "1" has been written to the
Command Register sample-and-hold bit (SH). This initiates
a self-calibration on the next clock cycle. The offset correc-
tion code is determined by a repeated sequence of auto-
zeroing the calibration comparator to the offset reference
and then comparing the DAC output to the offset reference
value. The end result is then averaged, Offset Two's Comple-
ment adjusted, and placed in the OCR. The gain correction
is done in a similar fashion except the correction is done
against V

REF

to eliminate common-mode errors. The FCR

result represents the gain code and is not Offset Two's
Complement adjusted.

The calibration function takes between 300ms and 500ms to
complete (for f

XIN

= 2.5MHz). Once calibration is initiated,

further writing of register bits is disabled until calibration
completes. The status of calibration can be verified by
reading the status of the Command Register Operation Mode
bits (MD1 through MD0). These bits will return to normal
mode "00" when calibration is complete.

Self-calibration can be done with the output isolated or
connected. This is done by setting (output connected) or
clearing (output isolated) the CALPIN bit in the CMR
register.

Output Mode

The DAC1220 can operate in either 16-bit mode or 20-bit
mode. The mode is determined by setting (20-bit) or clearing
(16-bit) the RES bit in the CMR register.

The output of the DAC1220 can be synchronously reset. By
setting the CLR bit in the CMR, the data input register is
cleared to zero. This will result in an output of 0V when
DF = 1 or V

REF

when DF = 0, assuming no calibration errors.

The settling time is determined by the DISF, RES, and
ADPT bits of the command register. The default state of
DISF = 0 and ADPT = 0 enables fast settling, unless the
output step is small (

40mV). However, the DAC1220 can

be forced to always use fast settling if the ADPT bit is
set to 1. If DISF is set to 1, all fast settling is disabled.

The SH bit of the CMR register determines if C

is internally

connected to V

REF

. By clearing the SH bit, C

is discon-

nected from V

REF

The CRST bit of the CMR register can be used to reset the
offset and calibration registers. By setting the CRST bit, the
contents of the calibration register are reset to 0.

REFERENCE INPUT

The reference input voltage of 2.5V can be directly con-
nected to V

REF

The recommended reference circuit for the DAC1220 is
shown in Figure 2.

FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1220.

OPA336

+5V

100k

REF1004-2.5

10k

0.10

0.1

0.10

To V

REF

100

DIGITAL OPERATION

SYSTEM CONFIGURATION

The DAC1220 is controlled by 8-bit instruction codes (INSR)
and 16-bit command codes (CMR) via the serial interface,
which is externally clocked.

The DAC1220 Microcontroller (MC) consists of an ALU
and a register bank. The MC has three states: power-on reset,
calibration, and normal operation. In the power-on reset
state, the MC resets all the registers to their default states. In
the calibration state, the MC performs offset and gain self-
calibration. In the normal state, the MC performs D/A
conversions.

The DAC1220 has five internal registers, as shown in
Table II. Two of these, the Instruction Register (INSR) and
the Command Register (CMR), control the operation of the
converter. The Instruction register utilizes an 8-bit instruc-
tion code to control the serial interface to determine whether
the next operation is either a read or a write, to control the
word length and to select the appropriate register to
read/write. Communication with the DAC1220 is controlled
via the INSR. The INSR is written as the first part of each
serial communication. The instruction that is sent determines
what type of communication will occur next. It is not
possible to read the INSR. The Command register has a 16-
bit command code to set up the DAC1220 operation mode,
resolution mode, settling mode and data format. The Data
Input Register (DIR) contains the value for the next conver-
sion. The Offset and Full-Scale Calibration Registers (OCR
and FCR) contain data used for correcting the internal
conversion value after it is placed into the DIR. The data in
these two registers may be the result of a calibration routine,
or they may be values which have been written directly via
the serial interface.

A3 A0 (Address) Bits--These four bits select the begin-
ning register location that will be read from or written to, as
shown in Table III. Each subsequent byte will be read from
or written to the next higher location (increment address).
If the BD bit in the Command register is set, each subse-
quent byte will be read from or written to the next lower
location (decrement address). This bit does not affect INSR
register or the write operation for the CMR register. If the
next location is reserved in Table III, the results are un-
known. Reading or writing continues until the number of
bytes specified by MB1 and MB0 have been transferred.

Instruction Register (INSR)

Each serial communication starts with the 8 bits of the INSR
being sent to the DAC1220. The read/write bit, the number
of bytes n, and the starting register address are defined, as
shown in Table III. When the n bytes have been transferred,
the instruction is complete. A new communication cycle is
initiated by sending a new INSR (under restrictions outlined
in the Interfacing section).

R/W (Read/Write) Bit--For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:

TABLE III. Instruction Register.

MSB

LSB

R/W

MB1

MB0

MB1, MB0 (Multiple Bytes) Bits--These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:

INSR

Instruction Register

8 Bits

DIR

Data Input Register

24 Bits

CMR

Command Register

16 Bits

OCR

Offset Calibration Register

24 Bits

FCR

Full-Scale Calibration Register

24 Bits

TABLE II. DAC1220 Registers.

MB1

MB0

1 Byte

2 Bytes

3 Bytes

R/W

Write

Read

Data Input Register Byte 2 MSB

Data Input Register Byte 1

Data Input Register Byte 0 LSB

Reserved

Command Register Byte 1 MSB

Command Register Byte 0 LSB

Reserved

Offset Cal Register Byte 2 MSB

Offset Cal Register Byte 1

Offset Cal Register Byte 0 LSB

Reserved

Full-Scale Cal Register Byte 2 MSB

Full-Scale Cal Register Byte 1

Full-Scale Cal Register Byte 0 LSB

Reserved

TABLE IV. A3 - A0 Addressing.

DAC1220

ADPT (Adaptive Filter Disable) Bit--The ADPT bit de-
termines if the adaptive filter is enabled or disabled. When
the Adaptive Filter is enabled, the DAC1220 does fast
settling only when there is an output step of larger than

40mV. For small changes in the data, fast settling is not

necessary. When ADPT = 1, the Adaptive Filter is disabled
and the DAC1220 will not look at the size of a step to
determine the necessity of using fast settling. In either case,
fast settling can be defeated if DISF = 1.

CALPIN (Calibration Pin) Bit--The Calibration Pin bit
determines if the output is isolated or connected during
calibration.

SH (Sample/Hold) Bit --The Sample-and-Hold bit deter-
mines if C

is internally connected to V

REF

. For best perfor-

mance, it is recommended to set this bit to 1.

CRST (Calibration Reset) Bit--The CRST bit resets the
offset and full-scale calibration registers.

RES (Resolution) Bit--The Resolution bit selects either
16-bit or 20-bit resolution.

Command Register (CMR)

The CMR controls all of the functionality of the DAC1220.
The new configuration is latched in on the negative transi-
tion of SCLK for the last bit of the last byte of data being
written to the command register. The organization of the
CMR is comprised of 16 bits of information in 2 bytes of 8
bits each.

MSB

Byte 1

ADPT

CALPIN

CRST

Byte 0

LSB

RES

CLR

DISF

MSB

MD1

MD0

NOTE: In order to obtain optimal performance, the default bit states for
the Command Register should be used (refer to Table VI). The only ex-
ception is the SH bit--the default bit state is 0, however, the bit should be
set to 1 for optimal performance.

TABLE V. Command Register.

CRST

OFF

Default

Reset

CLR (Clear) Bit--The CLR bit synchronously resets the
data input register to zero. The analog output will be based
on the DF bit--if 1, the output will be 0V; if 0, the output
will be V

REF

DF (Data Format) Bit--The DF bit controls the format of
the input data, shown in hexadecimal (either Offset Two's
Complement or Straight Binary), as shown:

DISF (Disable Fast Settling) Bit--The DISF bit disables
the fast settling option. If this bit is zero, the fast settling
performance is determined by the ADPT bit, the RES bit,
and the ADPT bit.

CLR

OFF

Default

DISF

Fast Settling (default)

Disable Fast Settling

Offset Two's

Straight

Complement

Binary

OUT

DF = 0

DF = 1

(default)

8000

0000

8000

REF

7FFF

FFFF

2 · V

REF

Input Code

BD (Byte Order) Bit--The BD bit controls the order in
which bytes of data are transferred (either most significant
byte first (MSBF) or least significant byte first (LSBF)), as
shown:

BD bit:

0 (default)

INSR

write only

MSBF

CMR

MSBF

LSBF

MSBF

DIR

MSBF

LSBF

MSBF

LSBF

OCR

MSBF

LSBF

MSBF

LSBF

FCR

MSBF

LSBF

MSBF

LSBF

Care must be observed in reading the Command Register if
the state of the BD bit is unknown. If a two byte read is
started at address 0100 with BD = 0, it will read the contents
at address 0100, then 0101. However, if BD = 1, it will read
from 0100, then 0011. If the BD bit is unknown, all reads of
the command register are best performed as read commands
of one byte.

RES

16-Bit

Default

20-Bit

ADPT

Enabled (default)

Disabled

CALPIN

Output Isolated

Default

Output Connected

Disconnected

Default

Connected

Recommended

read

write

Data Input Register (DIR)

The DIR is a 24-bit register which contains the digital input
value (see Table VIII). The register is latched on the falling
edge of the last bit of the last byte sent. The contents of the
DIR are then loaded into the modulator. This means that the
DIR register can be updated after sending 1, 2, or 3 bytes,
which is determined by the MB1 and MB0 bits in the
Instruction Register. The contents of the DIR can be Offset
Two's Complement or Straight Binary.

Offset Calibration Register (OCR)

The OCR is a 24-bit register containing the offset correction
factor that is used to apply a correction to the digital input
before it is transferred to the modulator. The results of the
self-calibration process will be written to this register.

The OCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate calibration,
a calibration can be performed, the results averaged, and a
more precise offset calibration value written back to the
OCR.

The actual OCR value after calibration will change from part
to part and with configuration, temperature, and power supply.

In addition, be aware that the contents of the OCR are not
used to directly correct the digital input. Rather, the correc-
tion is a function of the OCR value. This function is linear
and two known points can be used as a basis for interpolat-
ing intermediate values for the OCR.

The results of calibration are averaged, Offset Two's Comple-
ment adjusted, and placed in the OCR.

MSB (Bit Order) Bit--The MSB bit controls the order in
which bits within a byte of data are read or written (either
most significant bit first or least significant bit first) as
follows:

MD1 - MD0 (Operating Mode) Bits--The Operating Mode
bits control the calibration functions of the DAC1220. The
Normal mode is used to perform conversions. The Self-
Calibration mode is a one-step calibration sequence that
calibrates both the offset and full scale.

MSB

Byte 2

OCR23

OCR22

OCR21

OCR20

OCR19

OCR18

OCR17

OCR16

Byte 1

OCR15

OCR14

OCR13

OCR12

OCR11

OCR10

OCR9

OCR8

Byte 0

LSB

OCR7

OCR6

OCR5

OCR4

OCR3

OCR2

OCR1

OCR0

TABLE VI. Offset Calibration Register.

MSB

Byte 2

FCR23

FCR22

FCR21

FCR20

FCR19

FCR18

FCR17

FCR16

Byte 1

FCR15

FCR14

FCR13

FCR12

FCR11

FCR10

FCR9

FCR8

Byte 0

LSB

FCR7

FCR6

FCR5

FCR4

FCR3

FCR2

FCR1

FCR0

TABLE VII. Full-Scale Calibration Register.

MSB

Byte 2

DIR23

DIR22

DIR21

DIR20

DIR19

DIR18

DIR17

DIR16

Byte 1

DIR15

DIR14

DIR13

DIR12

DIR11

DIR10

DIR9

DIR8

Byte 0

LSB

DIR7

DIR6

DIR5

DIR4

DIR3

DIR2

DIR1

DIR0

TABLE VIII. Data Input Register.

Full-Scale Calibration Register (FCR)

The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the digital input before it
is transferred to the modulator. The contents of this register
will be the result of a self-calibration, or written to by the
user.

The FCR is both readable and writable via the serial inter-
face. For applications requiring an accurate system calibra-
tion, a system calibration can be performed, the results
averaged, and a more precise value written back to the FCR.

The actual FCR value after calibration will change from part
to part and with configuration, temperature, and power
supply.

In addition, be aware that the contents of the FCR are not
used to directly correct the digital input. Rather, the correc-
tion is a function of the FCR value. This function is linear
and two known points can be used as a basis for interpolat-
ing intermediate values for the FCR. The contents of the
FCR are in unsigned binary format. This is not affected by
the DF bit in the Command register.

MSB

MSB-First

Default

LSB-First

MD1

MD0

Normal Mode

Self-Cal

Sleep

DAC1220

SLEEP MODE

The Sleep Mode is entered after the bit combination 10 has
been written to the CMR Operation Mode bits (MD1 and
MD0). This mode ends when these bits are changed to a
value other than 10.

Communication with the DAC1220 can continue during
Sleep Mode. When a new mode (other than Sleep) has been
entered, the DAC1220 will execute a very brief internal
power-up sequence of the analog and digital circuitry. In
addition, the settling of the external V

REF

and other circuitry

must be taken into account to determine the amount of time
required to resume normal operation.

The output is turned off in sleep mode.

SERIAL INTERFACE

The DAC1220 includes a flexible serial interface which can
be connected to microcontrollers and digital signal proces-
sors in a variety of ways. Along with this flexibility, there is
also a good deal of complexity. This section describes the
trade-offs between the different types of interfacing methods
in a top-down approach--starting with the overall flow and
control of serial data, moving to specific interface examples,
and then providing information on various issues related to
the serial interface.

SCLK

Reset On

Falling Edge

FIGURE 3. Resetting the DAC1220.

: > 512 · t

XIN

< 800 · t

XIN

: > 10 · t

XIN

: > 1024 · t

XIN

< 1800 · t

XIN

2048 · t

XIN

< 2400 · t

XIN

Reset, Power-On Reset and Brown-Out

The DAC1220 contains an internal power-on reset circuit. If
the power supply ramp rate is greater than 50mV/ms, this
circuit will be adequate to ensure the device powers up
correctly. Due to oscillator settling considerations, commu-
nication to and from the DAC1220 should not occur for at
least 25ms after power is stable.

If this requirement cannot be met or if the circuit has brown-
out considerations, the timing diagram of Figure 3 can be
used to reset the DAC1220. This accomplishes the reset by
controlling the duty cycle of the SCLK input.

Sleep mode is the default state after power on or reset. The
output is high impedance during sleep mode.

I/O Recovery

If serial communication stops during an instruction or data
transfer for longer than 100ms (for f

XIN

= 2.5MHz), the

DAC1220 will reset its serial interface. This will not affect
the internal registers. The main controller must not continue
the transfer after this event, but must restart the transfer from
the beginning. This feature is very useful if the main control-
ler can be reset at any point. After reset, simply wait 200ms
(for f

XIN

= 2.5MHz) before starting serial communication.

Isolation

The serial interface of the DAC1220 provides for simple
isolation methods. An example of an isolated two-wire
interface is shown in Figure 4.

OUT

DGND

DNC

SCLK

SDIO

AGND

REF

OUT

DAC1220

12pF

XTAL

OUT

REF

P1.1

P1.0

8051

Opto

Coupler

Opto

Coupler

Isolated

Power

= DGND

= AGND

= Isolated

FIGURE 4. Isolation for Two-Wire Interface

Using CS

The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
condition. They only become active when serial data is
being transmitted from the DAC1220. If the DAC1220 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.

If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1220.

TIMING

The maximum serial clock frequency cannot exceed the
DAC1220 X

frequency divided by 10. Table IX and

Figures 5 through 9 define the basic digital timing character-
istics of the DAC1220. Figure 5 and the associated timing
symbols apply to the X

input signal. Figures 6 through 9

and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.

TABLE IX. Digital Timing Characteristics.

SYMBOL

DESCRIPTION

MIN

NOM

MAX

UNITS

XIN

Clock Frequency

2.5

MHz

XIN

Clock Period

400

1000

Clock High

0.4 · t

XIN

Clock LOW

0.4 · t

XIN

SCLK HIGH

5 · t

XIN

SCLK LOW

5 · t

XIN

Data In Valid to SCLK Falling Edge (Setup)

SCLK Falling Edge to Data In Not Valid (Hold)

Data Out Valid After Rising Edge of SCLK (Hold)

SCLK Rising Edge to New Data Out Valid (Delay)

(1)

Falling Edge of Last SCLK for INSR to Rising Edge of First

13 · t

XIN

SCLK for Register Data

Falling Edge of CS to Rising Edge of SCLK

11 · t

XIN

Falling Edge of Last SCLK for INSR to SDIO as Output

8 · t

XIN

10 · t

XIN

SDIO as Output to Rising Edge of First SCLK for Register Data

4 · t

XIN

Falling Edge of Last SCLK for Register Data to SDIO Tri-State

4 · t

XIN

6 · t

XIN

Falling Edge of Last SCLK for Register Data to Rising Edge

41 · t

XIN

of First SCLK of next INSR (CS Tied LOW)

Rising Edge of CS to Falling Edge of CS (Using CS)

22 · t

XIN

NOTE: (1) With 10pF load.

FIGURE 10. Flowchart for Writing and Reading Register Data.

Start

Writing

Start

Reading

External device

generates 8

serial clock cycles

and transmits

instruction register

data via SDIO

CS taken HIGH

for t

periods

minimum

(or CS tied LOW)

External device

generates n

serial clock cycles

and transmits

specified

via SDIO

state

instructions?

End

HIGH

Yes

LOW

Is next

instruction

a read?

Yes

state

From Read

flowchart

HIGH

LOW

To Read

flowchart

External device

generates 8 serial

clock cycles and

transmits instruction

via SDIO

SDIO input to

output transition

state

instructions?

End

HIGH

Yes

LOW

Is next

instruction

a Write?

Yes

state

To Write

flowchart

HIGH

LOW

To Write

flowchart

External device

generates n serial

clock cycles and

receives specified

SDIO transitions to

tri-state condition

CS taken HIGH

for t

periods

minimum

(or CS tied LOW)

DAC1220

LAYOUT

POWER SUPPLIES

The DAC1220 requires the digital supply (DV

) to be no

greater than the analog supply (AV

) +0.3V. In the major-

ity of systems, this means that the analog supply must come
up first, followed by the digital supply and V

REF

. Failure to

observe this condition could cause permanent damage to the
DAC1220.

Inputs to the DAC1220, such as SDIO or V

REF

, should not

be present before the analog and digital supplies are on.
Violating this condition could cause latch-up. If these sig-
nals are present before the supplies are on, series resistors
should be used to limit the input current.

The best scheme is to power the analog section of the design
and AV

of the DAC1220 from one +5V supply, and the

digital section (and DV

) from a separate +5V supply. The

analog supply should come up first. This will ensure that
SCLK, SDIO, CS and V

REF

do not exceed AV

, that the

digital inputs are present only after AV

has been estab-

lished, and that they do not exceed DV

The analog supply should be well regulated and low noise.
For designs requiring very high resolution from the DAC1220,
power supply rejection will be a concern. See the "PSRR vs
Frequency" curve in the Typical Performance Curves sec-
tion of this data sheet for more information.

The requirements for the digital supply are not as strict.
However, high frequency noise on DV

can capacitively

couple into the analog portion of the DAC1220. This noise
can originate from switching power supplies, very fast
microprocessors, or digital signal processors.

If one supply must be used to power the DAC1220, the
AV

supply should be used to power DV

. This connec-

tion can be made via a 10

resistor which, along with the

decoupling capacitors, will provide some filtering between
DV

and AV

. In some systems, a direct connection can

be made. Experimentation may be the best way to determine
the appropriate connection between AV

and DV

GROUNDING

The analog and digital sections of the design should be
carefully and cleanly partitioned. Each section should have
its own ground plane with no overlap between them. AGND
should be connected to the analog ground plane, as well as
all other analog grounds. DGND should be connected to the
digital ground plane, and all digital signals referenced to this
plane.

The DAC1220 pinout is such that the converter is cleanly
separated into an analog and digital portion. This should
allow simple layout of the analog and digital sections of the
design.

For a single converter system, AGND and DGND of the
DAC1220 should be connected together, underneath the
converter. Do not join the ground planes. Instead, connect
the two with a moderate signal trace. For multiple convert-
ers, connect the two ground planes at one location, as central
to all of the converters as possible. In some cases, experi-
mentation may be required to find the best point to connect
the two planes together. The printed circuit board can be
designed to provide different analog/digital ground connec-
tions via short jumpers. The initial prototype can be used to
establish which connection works best.

DECOUPLING

Good decoupling practices should be used for the DAC1220
and for all components in the design. All decoupling capaci-
tors, and specifically the 0.1

F ceramic capacitors, should

be placed as close as possible to the pin being decoupled. A
1

F to 10

F capacitor, in parallel with a 0.1

F ceramic

capacitor, should be used to decouple AV

to AGND. At

a minimum, a 0.1

F ceramic capacitor should be used to

decouple DV

to DGND, as well as for the digital supply

on each digital component.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC1220

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC1220