DAC2815
A
20k
20k
20k
20k
10k
10k
Logic
17
18
14
13
20
16
19
15
10
12
8
11
28
+V Out
REF
Inv In
Inv Out
V In
REF
BPO A
V A
OUT
BPO B
V B
OUT
+V
L
+V
S
V
S
AGND
DGND
10V
Ref
DAC A
DAC B
DAC2815
3
A
1
A
2
8-Bit
Port and
Control In
FEATURES
q
COMPLETE DUAL DAC --
INCLUDES INTERNAL REFERENCES AND
OUTPUT AMPLIFIERS
q
GUARANTEED SPECIFICATIONS OVER
TEMPERATURE
q
GUARANTEED MONOTONIC OVER
TEMPERATURE
DESCRIPTION
The DAC2815 is one in a family of dual and quad 12-
bit digital-to-analog converters (DACs). Serial, 8-bit,
12-bit interfaces are available.
The DAC2815 is complete. It contains CMOS logic,
switches, a high-performance buried-zener reference,
and low-noise bipolar output amplifiers. No external
components are required for either unipolar 0 to 10V,
0 to 10V, or bipolar
10V output ranges.
The DAC2815 has a 2-byte (8 + 4) double-buffered
interface. Data is first loaded (level transferred) into
the input registers in two steps for each DAC. Then
both DACs are updated simultaneously. The DAC has
an asynchronous clear control for reset to unipolar or
bipolar zero depending on the mode selected. This
feature is useful for power-on reset or system calibra-
tion. The DAC2815 is packaged in a 28-pin plastic
DIP rated for the 40
C to +85
C extended industrial
temperature range.
High-stability laser-trimmed thin film resistors assure
high reliability and true 12-bit integral and differential
linearity over the full specified temperature range.
DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER (8-Bit Port Interface)
q
HIGH-SPEED 8 + 4-BIT PARALLEL
INTERFACE
q
LOW POWER: 300mW (150mW/DAC)
q
LOW GAIN DRIFT: 5ppm/
C
q
LOW NONLINEARITY:
1/2 LSB max
q
UNIPOLAR OR BIPOLAR OUTPUT
q
CLEAR/RESET TO UNIPOLAR OR
BIPOLAR ZERO
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1991 Burr-Brown Corporation
PDS-1110B
Printed in U.S.A. October, 1993
DAC2 815
2
SPECIFICATIONS
, Guaranteed over T
A
= 40
C to +85
C unless otherwise specified.
ELECTRICAL
Specifications as shown for V
S
=
12V or
15V, V
L
= +5V, and R
L
= 2k
unless otherwise noted.
DAC2815AP
DAC2815BP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Resolution
12
*
Bits
V
IH
(Input High Voltage)
2
5
*
*
V
V
IL
(Input Low Voltage)
0
0.8
*
*
V
I
IN
( Input Current)
T
A
= 25
C
1
*
A
T
A
= 40
C to +85
C
10
*
A
C
IN
(Input Capacitance)
0.8
*
pF
ACCURACY
Integral, Relative Linearity
(1)
1
1/2
LSB
Differential Nonlinearity
(2)
T
A
= 25
C
1
*
LSB
T
A
= 40
C to +85
C
+1.5/1
1
LSB
Unipolar Offset Error
T
A
= +25
C
1
0.5
mV
T
A
= 40
C TO +85
C
3
*
mV
Bipolar Zero Error
20
10
mV
Gain Error Unipolar, Bipolar
With Internal or External 10.0V Ref
0.2
0.15
%
Power Supply Sensitivity
(3)
V
S
=
11.4V to
18V,
30
*
ppmFSR/V
V
L
= +4.5V to +5.5V
TEMPERATURE DRIFT
Gain Drift Unipolar, Bipolar
5
30
*
20
ppm/
C
Unipolar Offset Drift
0.1
5
*
*
ppmFSR/
C
Bipolar Zero Drift
5
15
*
8
ppmFSR/
C
REFERENCE OUTPUT
Output Voltage
+9.980
+10
+10.020
+9.985
*
+10.015
V
Reference Drift
2
30
*
20
ppm/
C
Output Current
T
A
= 25
C
+10/5
*
mA
T
A
= 40
C to +85
C
+6.5/5
*
mA
Max Load Capacitance (For Stability)
500
*
pF
Short Circuit Current
20
*
mA
Load Regulation
40
*
ppm/mA
(
V
OUT
vs
I
LOAD
)
Supply Regulation
5
*
ppm/V
(
V
OUT
vs
V
S
)
INVERTER
10V Reference
(4)
, Inverter Output
10.020
10
9.980
10.015
*
9.985
V
10V Reference Drift
30
20
ppm/
C
DC Output Impedance
0.1
*
Output Current
7
*
mA
Max Load Capacitance (For Stability)
200
*
pF
Short Circuit Current
30
*
mA
REFERENCE INPUT
Reference Input Resistance
3.5
5
*
*
k
Inverter Input Resistance
7
10
*
*
k
BPO Input Resistance
14
20
*
*
k
Reference Input Range
10
*
V
ANALOG SIGNAL OUTPUTS
Voltage Range
V
S
+ 1.4
+V
S
1.4
*
*
V
DC Output Impedance
0.1
*
Output Current
5
*
mA
Max Load Capacitance (For Stability)
V
OUT
500
*
pF
Short Circuit Current
30
*
mA
DYNAMIC PERFORMANCE
(5)
C
L
= 100pF
Unipolar Mode Settling Time
To 1/2 LSB of Full Scale
2.5
10
*
*
s
Bipolar Mode Settling Time
To 1/2 LSB of Full Scale
3.5
10
*
*
s
Slew Rate
10
*
V/
s
Small-Signal Bandwidth
3
*
MHz
ANALOG GROUND CURRENT
(Code Dependent)
2
*
mA
DIGITAL CROSSTALK
Full Scale Transition
3
*
nV-s
C
L
= 100pF
D/A GLITCH IMPULSE
30
*
nV-s
DAC2 815
3
POWER SUPPLY
+V
S
and V
S
11.4
15
18
*
*
*
V
+V
L
4.5
5
5.5
*
*
*
V
+I
S
+10
+13.5
*
*
mA
I
S
10
13.5
*
*
mA
+I
L
Digital Inputs = 0V or +V
L
0.2
1
*
*
mA
+I
L
Digital Inputs = V
IL
or V
IH
5
*
mA
Total Power, All DACs
300
410
*
*
mW
TEMPERATURE RANGE
Specified
40
+85
*
*
C
Operating
40
+85
*
*
C
Thermal Resistance,
JA
75
*
C/W
SPECIFICATIONS
(CONT)
, Guaranteed over T
A
= 40
C to +85
C unless otherwise specified.
ELECTRICAL
Specifications as shown for V
S
=
12V or
15V, V
L
= +5V, and R
L
= 2k
unless otherwise noted.
DAC2815AP
DAC2815BP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes voltage output DAC, voltage reference, and reference
inverter. (4) Inverter output with inverter input connected to +V
REF
. (5) Guaranteed but not tested.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
ORDERING INFORMATION
LINEARITY ERROR
MODEL
(LSB)
DAC2815AP
1
DAC2815BP
1/2
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
DAC2815AP
28-Pin Plastic DIP
215
DAC2815BP
28-Pin Plastic DIP
215
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
+V
L
to AGND ................................................................................. 0V, +7V
+V
L
to DGND ................................................................................ 0V, +7V
+V
S
to AGND .............................................................................. 0V, +18V
V
S
to AGND ............................................................................... 0V,18V
AGND to DGND ................................................................................
0.3V
Any digital input to DGND .............................................. 0.3V, +V
L
+0.3V
Ref In to AGND ..................................................................................
25V
Ref In to DGND ..................................................................................
25V
Storage Temperature Range .......................................... 55
C to +125
C
Operating Temperature Range ......................................... 40
C to +85
C
Lead Temperature (soldering, 10s) ................................................ +300
C
Junction Temperature .................................................................... +155
C
Output Short Circuit ................................... Continuous to common or
V
S
Reference Short Circuit .............................. Continuous to common or +V
S
DAC2 815
4
PIN DESIGNATIONS
PIN
DESCRIPTOR
FUNCTION
PIN
DESCRIPTOR
FUNCTION
1
D
6
Data bit 6 input
28
DGND
Digital common
2
D
7
Data bit 7 input
27
D
5
Data bit 5 input
3
A
0
Address 0 input
26
D
4
Data bit 4 input
4
A
1
Address 1 input
25
D
3
Data bit 3 input
5
CLR
Asychronous input reset to zero
24
D
2
Data bit 2 input
6
MODE
Selection input for unipolar or bipolar reset to zero
23
D
1
Data bit 1 input
7
CS
Chip select enable, DAC A and DAC B
22
D
0
Data bit 0 input
8
V
S
Negative analog power supply, 15V input
21
WR
Write input, DAC A and DAC B
9
LE
Latch data enable, DAC A and DAC B
20
BPO A
Bipolar offset input, DAC A
10
+V
L
Positive logic power supply, +5V input
19
BPO B
Bipolar offset input, DAC B
11
AGND
Analog common
18
Inv In
Inverter (A3) input
12
+V
S
Positive analog power supply, +15V input
17
+V
REF
Out
Reference voltage, +10V output
13
V
REF
In
Reference voltage input
16
V
OUT
A
Analog output voltage, DAC A
14
Inv Out
Inverter (A
3
) output
15
V
OUT
B
Analog output voltage, DAC B
PIN CONFIGURATION
TYPICAL PERFORMANCE CURVES
T
A
= +25
C, V
S
=
12V or
15V, V
L
= +5V unless otherwise noted.
DGND
D
5
D
4
D
3
D
2
D
1
D
0
WR
BPO A
BPO B
Inv In
+V
REF
Out
V
OUT
A
V
OUT
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D
6
D
7
A
0
A
1
CLR
MODE
CS
V
S
LE
+V
L
AGND
+V
S
V
REF
In
Inv Out
DAC2815
Top View
PSRR vs FREQUENCY (Bipolar Mode)
80
70
60
50
40
30
20
10
0
PSRR (dB)
1k
10k
100k
1M
Frequency (Hz)
V
OUT
= +10V
V
OUT
= 0V
NOISE vs BANDWIDTH (Bipolar Mode)
250
200
150
100
50
0
Voltage Noise (Vrms)
100
1k
10k
100k
1M
Frequency (Hz)
V
OUT
= +10V
FFF
HEX
V
OUT
= 0V
800
HEX
Top View
DIP
DAC2 815
5
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C, V
S
=
12V or
15V, V
L
= +5V unless otherwise noted.
V
OUT
LE
V
OUT
B
V
OUT
A
LE
NOTE: Crosstalk is dominated by digital crosstalk/
feedthrough of the LE signal.
V
OUT
OUTPUT VOLTAGE SWING vs RESISTOR LOAD
Load Resistance ( )
25
20
15
10
5
0
V
OUT
(Vp-p)
10
100
1k
10k
V
S
= 15V
V
L
= 5V
10V REF
CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR
vs TEMPERATURE
+1.5
+1.0
+0.5
0
0.5
1.0
1.5
Bipolar Offset and Zero Error (mV)
40
20
0
20
40
60
80
Temperature (C)
+0.015
+0.01
+0.005
0
0.005
0.01
0.015
Gain Error (%)
Bipolar Offset
Gain Error
Bipolar Zero
0V
+5V
0V
FULL-SCALE OUTPUT SWING
UNIPOLAR (10V Step)
Time (2s/div)
V
OUT
(5V/div)
0V
0V
+5V
0V
CROSSTALK (Bipolar Mode)
Time (500ns/div)
V
OUT
FULL-SCALE OUTPUT SWING
BIPOLAR (20V Step)
Time (2s/div)
V
OUT
(5V/div)
POWER SUPPLY CURRENT vs TEMPERATURE
11.8
11.6
11.4
11.2
11
10.8
10.6
10.4
I
S
(mA) Analog Supply
40
20
0
20
40
60
80
Temperature (C)
+I
L
(mA) Logic Supply
3.5
3
2.5
2
1.5
1
0.5
0
+I
L
(All Logic Inputs = 2V)
I
S
+I
L
(All Logic Inputs = 0V or V
L
)
DAC2 815
6
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
C, V
S
=
12V or
15V, V
L
= +5V unless otherwise noted.
V
OUT
LE
V
OUT
LE
V
OUT
LE
V
OUT
LE
V
OUT
LE
NOTE: Data transition 800
HEX
to 7FF
HEX
.
DAC output noise due to activity on digital inputs
with latch disabled.
V
OUT
0V
+10V
+5V
SETTLING TIME
BIPOLAR (10V to +10V)
Time (1s/div)
V Around +10V (2mV/div)
SETTLING TIME
BIPOLAR (+10V to 10V Step)
Time (2s/div)
V Around 10V (2mV/div)
0V
+5V
10V
0V
+5V
0V
+10V
+5V
0V
MAJOR CARRY GLITCH
Time (1s/div)
V
OUT
(20mV/div)
0V
+5V
0V
DIGITAL FEEDTHROUGH
Time (500ns/div)
V
OUT
(5mV/div)
0V
SETTLING TIME
UNIPOLAR (0V to +10V Step)
Time (1s/div)
V Around +10V (1mV/div)
SETTLING TIME
UNIPOLAR (+10V to 0V STEP)
Time (1s/div)
V Around 10V (1mV/div)
DAC2 815
7
TIMING CHARACTERISTICS
+V
L
= +5V, T
A
= 40
C to +85
C.
PARAMETER
MINIMUM
t
1
--Address Valid to Write Setup Time
10ns
t
2
--Address Valid to Write Hold Time
10ns
t
3
--Data Setup Time
30ns
t
4
--Data Hold Time
10ns
t
5
--Chip Select to LE
0ns
or Write Setup Time
t
6
--Chip Select to LE
0ns
or Write Hold Time
t
7
--Write Pulse Width
40ns
t
8
--Clear Pulse Width
40ns
t
5
t
6
t
7
t
8
CS
LE, WR
CLR
0V
5V
0V
5V
5V
5V
NOTES: (1) All input signal rise and fall times are measured
from 10% to 90% of +5V. t = t = 5ns.
R
F
IH
IL
2
t
1
t
3
t
4
t
2
0V
0V
0V
5V
DATA
A
0
-A
1
(2) Timing measurement reference level is V + V .
FUNCTIONAL BLOCK DIAGRAM,
DAC2815 -- Dual 12-bit DAC, 8-bit Port
INTERFACE LOGIC TRUTH TABLE
MODE
CLR
LE
CS
WR
A
1
A
0
FUNCTION
X
1
1
0
0
0
0
DAC A LS Input Register Loaded with D7-D0 (LSB)
X
1
1
0
0
0
1
DAC A MS Input Register Loaded with D3-(MSB)-D0
X
1
1
0
0
1
0
DAC B LS Input Register Loaded with D7-D0 (LSB)
X
1
1
0
0
1
1
DAC B MS Input Register Loaded with D3-(MSB)-D0
X
1
0
0
1
X
X
DAC A, DAC B Registers Updated Simultaneously from Input Registers
X
1
0
0
0
X
X
DAC A, DAC B Registers are Transparent
X
1
X
1
X
X
X
No Data Transfer
X
1
1
X
1
X
X
No Data Transfer
0
0
X
X
X
X
X
All Registers Cleared
1
0
X
X
X
X
X
Input Registers Cleared = 000
HEX
, DAC Registers = 800
HEX
NOTE: X = Don't care.
10k
10k
20k
20k
20k
20k
19
15
BPO B
V B
OUT
DAC B
20
16
BPO A
V A
OUT
DAC A
14 Inv Out
Control
Logic
12-Bit
Latch
Register
12-Bit
Latch
Register
Bits 0-11
Bits 0-11
17
28
11
10
6
MODE
A
0
WR
CLR
5
+V Out
REF
Inv In
27
Data In
13
V In
REF
+10V
Voltage
Reference
CS
21
7
LE
9
3
A
3
A
2
A
1
8-Bit
Input
Register
Bits 0 - 7
4-Bit
Input
Register
Bits 8 -11
8-Bit
Input
Register
Bits 0 - 7
4-Bit
Input
Register
Bits 8 -11
12
8
+V
L
V
S
AGND
DGND
+V
S
1
2
22
4
A
1
18
DAC2 815
8
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
All digital inputs of the DAC2815 are TTL and 5V CMOS
compatible. Input codes for the DAC2815 are either USB
(Unipolar Straight Binary) or BOB (Bipolar Offset Binary)
depending on the mode of operation. See Figure 3 for
10V
bipolar connection. See Figures 4 and 5 for 0 to 10V and 0
to 10V unipolar connections.
INTEGRAL OR RELATIVE LINEARITY
This term, also known as end point linearity, describes the
transfer function of analog output to digital input code.
Integral linearity error is the deviation of the analog output
versus code transfer function from a straight line drawn
through the end points.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1
LSB change in the output voltage when the input code
changes by 1 LSB. A differential nonlinearity specification
of
1 LSB maximum guarantees monotonicity.
UNIPOLAR OFFSET ERROR
The output voltage for code 000
HEX
when the DAC is in the
unipolar mode of operation.
BIPOLAR ZERO ERROR
The output voltage for code 800
HEX
when the DAC is in the
bipolar mode of operation.
GAIN ERROR
The deviation of the output voltage span (V
MAX
V
MIN
) from
the ideal span of 10V 1 LSB (unipolar mode) or 20V 1
LSB (bipolar mode). The gain error is specified with and
without the internal +10V reference error included.
OUTPUT SETTLING TIME
The time required for the output voltage to settle within a
percentage-of-full-scale error band for a full scale transition.
Settling to
0.012% (1/2 LSB) is specified for the DAC2815.
UNIPOLAR AND BIPOLAR
OUTPUTS FOR SELECTED INPUT
DIGITAL INPUT
UNIPOLAR (USB)
BIPOLAR (BOB)
FFF
HEX
+Full scale
+Full scale
800
HEX
+1/2 Full scale
Zero
7FF
HEX
+1/2 Full scale 1 LSB
Zero 1 LSB
000
HEX
Zero
Full scale
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC--see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nVs. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs--see Typical Performance
Curves.
OPERATION
Depending on the address selected, the 4 MSBs or the 8
LSBs are written into the appropriate input register for each
DAC when the WR signal is brought low. This data is
latched in the input register when the WR goes high. Data
are then transferred from the input registers to the DAC latch
registers by bring LE low. The data are latched in the DAC
latch registers when LE goes high. Both DACs are updated
simultaneously.
When CLR is brought low, the input registers are cleared to
000
HEX
(10V), while the DAC registers = 800
HEX
. If LE is
brought low, the DACs are updated with 000
HEX
resulting in
10V (bipolar) or 0V (unipolar) on the output.
CIRCUIT DESCRIPTION
Each of the two DACs in the DAC2815 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a reference inverter
(for a 10.0V reference) are shared by both DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V
REF
.
Current from the ladder is switched either to I
OUT
or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
D11
(MSB)
D10
D9
D0
(LSB)
AGND
I
R
R
R
2R
2R
2R
2R
2R
R
OUT
V
REF
R
FB
DAC2 815
9
R
GND
DAC A
DAC B
DAC A
DAC B
R
GND
V A
OUT
V B
OUT
V A
OUT
V B
OUT
AGND
AGND
DAC2815
DAC2815
NOTE: Ideally R = 0
GND
FIGURE 2. Recommended Ground Connections for Multiple DAC packages.
digital input code. This makes the resistance at V
REF
constant
(it can be driven by either a voltage or current reference).
The reference can be either positive or negative polarity with
a range of up to
10V.
CMOS switches included in series with the ladder terminat-
ing resistor and the feedback resistor, R
FB
, compensate for
the temperature drift of the ladder switch ON resistance.
The output op amps are connected as transimpedance ampli-
fiers to convert the DAC-cell output current into an output
voltage. They have been specially designed and compen-
sated for precision and fast settling in this application.
POWER SUPPLY CONNECTIONS
The DAC2815 is specified for operation with power sup-
plies of V
L
= +5V and V
S
= either
12V or
15V. Even with
the V
S
supplies at
11.4V the DACs can swing a full
10V.
Power supply decoupling capacitors (1
F tantalum) should
be located close to the DAC power supply connections.
Separate digital and analog ground pins are provided to
permit separate current returns. They should be connected
together at one point. Proper layout of the two current
returns will prevent digital logic switching currents from
degrading the analog output signal. The analog ground
current is code dependent so the impedance to the system
reference ground must be kept to a minimum. Connect
DACs as shown in Figure 2 or use a ground plane to keep
ground impedance less than 0.1
for less than 0.1LSB error.
10V REFERENCE
An internal inverting amplifier (Gain = 1.0V/V) is
provided to invert the +10V reference. Connect +V
REF
Out to
Inv In for a 10V reference at Inv Out.
OUTPUT RANGE CONNECTIONS
10V Output Range
For a
10V bipolar outputs connect the DAC2815 as shown
in Figure 3. Connect the MODE to logic high (+5V) for reset
to bipolar zero. With MODE connected low (GND) reset
will be to Full-Scale.
0 To +10V Output Range
For 0 to +10V unipolar outputs connect the DAC2815 as
shown in Figure 4. Connect the MODE to logic low (GND)
for reset to unipolar zero.
0 To 10V Output Range
For 0 to 10V unipolar outputs connect the DAC2815 as
shown in Figure 5. Connect the MODE to logic low (GND)
for reset to unipolar zero.
CONNECTION TO DIGITAL BUS
DAC2815s can easily be connected to a
processor bus.
Decode your address lines to derive the control signals
shown in Figure 6. Only one LATCH signal is required for
a system where all DAC2815s are updated simultaneously.
If you want to update DAC2815s independently, use sepa-
rate LATCH signals. The LATCH and WRITE signals can
be brought low simultaneously to update the DAC registers
with the same processor instruction that writes the final 8-bit
data word the DAC input registers.
DAC2 815
10
20k
20k
20k
20k
10k
10k
V A
OUT
V B
OUT
10V
Ref
DAC A
DAC B
DAC2815
+
+
10
12
8
15V
1F
+15V
1F
1F
+5V
15
19
16
20
13
14
18
17
28
11
DGND
AGND
A
3
A
1
A
2
+
6
MODE
8-Bit
Port and
Control In
20k
20k
20k
20k
10k
A
10k
V A
OUT
V B
OUT
10V
Ref
DAC A
DAC B
DAC2815
+
+
10
12
8
15V
1F
+15V
1F
1F
+5V
15
19
16
20
13
14
18
17
28
11
DGND
AGND
3
A
1
A
2
+
6
MODE
+5V
8-Bit
Port and
Control In
FIGURE 3. Analog Connections for
10V DAC Output.
FIGURE 4. Analog Connections for 0 to +10V DAC Output.
DAC2 815
11
20k
20k
20k
20k
V A
OUT
V B
OUT
10V
Ref
DAC A
DAC B
DAC2815
+
10
12
8
15V
1F
+15V
1F
1F
+5V
15
19
16
20
13
17
28
11
DGND
AGND
A
1
A
2
+
+
MODE 6
8-Bit
Port and
Control In
FIGURE 5. Analog Connections for 0 to 10V DAC Output.
FIGURE 6. Logic Connection for Multiple DAC2815
Packages.
Data In
WR
LE
A
0
CS
CS
7
1-2, 22-27
21
9
3
7
Data
WRITE 1
A
0
DAC2815
A
1
4
WRITE 2
Data In
WR
LE
A
0
1-2, 22-27
21
9
3
A
1
4
DAC2815
LATCH
A
1
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