12-Bit 256MHz Monolithic
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q
12-BIT RESOLUTION
q
256MHz UPDATE RATE
q
73dB HARMONIC DISTORTION AT 10MHz
q
LASER TRIMMED ACCURACY: 1/2LSB
q
5.2V SINGLE POWER SUPPLY
q
EDGE-TRIGGERED LATCH
q
LOW GLITCH: 5.6pVs
q
WIDEBAND MULTIPLYING REFERENCE
INPUT
q
50
OUTPUT IMPEDANCE
APPLICATIONS
q
DIRECT DIGITAL SYNTHESIS
q
ARBITRARY WAVEFORM GENERATION
q
HIGH RESOLUTION GRAPHICS
q
COMMUNICATIONS LOCAL
OSCILLATORS
Spread Spectrum/Frequency Hopping
Base Stations
Digitally Tuned Receivers
DESCRIPTION
The DAC600 is a monolithic, high performance digi-
tal-to-analog converter for high frequency waveform
generation. The internal segmentation and latching
minimize output glitch energy and maximizes AC
performance. Resistor laser trimming provides for
excellent DC linearity.
The ECL compatibility provides for low digital noise
at high update rates. The complementary 50
outputs
and low output capacitance simplifies transmission
line design and filtering at the output.
The DAC600 combines precision thin film and bipolar
technology to create a high performance, cost effec-
tive solution for modern waveform synthesis.
50
12-Bit
ECL Lines
20mA
CLK
Edge Triggered Bit Latch
50
V
OUT
V
OUT
V
REF
R
OFFSET
Control
Amplifier
CLK
LGND
DAC600
DEMO BOARD
AVAILABLE
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1992 Burr-Brown Corporation
PDS-1153E
Printed in U.S.A. November, 1996
DAC600
2
T
Same as specification for DAC600AN.
NOTES: (1) Linearity tests are measured into a virtual ground (op amp). (2) Gain error in % is calculated by: GE (%) =
(3) Settling time is influenced by the load due to fast edge speeds. Use good transmission line techniques
for best results. (4) Spurious free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth f
CLK
/2
C
,
unless otherwise specified.
SPECIFICATIONS
ELECTRICAL
At +25
C V
REF
= +1.0V, V
EEA
= V
EED
= 5.2V, unless otherwise noted.
DAC600AN
DAC600BN
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Logic
12 Parallel Input Lines, ECL
Resolution
12
T
Bits
ECL Logic Input Levels: V
IL
Logic "0"
Full
1.48
1.95
2
T
T
T
V
I
IL
Full
2
T
A
V
IH
Logic "1"
Full
1.1
0.75
0
T
T
T
V
I
IH
Full
200
T
A
DIGITAL TIMING
Input Data Rate
Full
DC
256
T
T
MHz
CLK Pulse Width High or Low
Full
1.95
T
ns
Set-up Time
Full
1.5
1.0
T
T
ns
Hold Time (Referred to CLK)
Full
1.9
1.7
T
T
ns
Propagation Delay
Full
2
T
ns
ANALOG OUTPUT
Bipolar Output Current
R
L
= 0
Full
19
20
21
T
T
T
mA
Output Resistance
Full
47.5
50
52.5
49
T
51
Output Capacitance
Full
15
T
pF
CONTROL AMPLIFIER
Input Resistance
Full
800
T
Full Power Bandwidth
3dB
Full
10
T
MHz
Offset
+25
C
0
1
0
0.5
mV
Input Reference Range
Full
100mV
1.25
T
T
V
TRANSFER CHARACTERISTICS
Integral Linearity Error
(1)
: V
OUT NOT
Best Fit Straight Line
+25
C
0.012
0.024
0.006
0.012
%FSR
V
OUT NOT
Full
0.024
0.036
0.012
0.024
%FSR
V
OUT
+25
C
0.1
0.1
%FSR
Differential Linearity Error
(1)
: V
OUT NOT
+25
C
0.024
0.012
%FSR
V
OUT NOT
Full
0.036
0.024
%FSR
V
OUT
+25
C
0.1%
0.1%
%FSR
12-Bit Monotonicity
+25
C
Guaranteed
Guaranteed
Full
Typical
Guaranteed
Output Offset Current: V
OUT NOT
Bits 1-12 HIGH
+25
C
75
150
50
100
A
V
OUT NOT
Full
57
150
50
100
A
Gain Error
(2)
+25
C
0.5
1.5
0.5
1.0
%
Full
1.3
2.0
1.1
2.0
%
Output Leakage Current
V
REF
= 0V, Bits 1-12 LOW, V
OUT NOT
+25
C
10
75
5
50
A
TIME DOMAIN PERFORMANCE
Glitch Energy
Major Carry
+25
C
5.6
T
pVs
Fall Time
90% to 10%
+25
C
510
T
ps
Rise Time
10% to 90%
+25
C
770
T
ps
Settling Time
(3)
0.1% FSR
Major Carry, 1 LSB Change
Full
4
T
ns
0.024% FSR
Full
15
T
ns
DYNAMIC PERFORMANCE
Spurious Free Dynamic Range
(4)
f
O
= 1MHz
f
CLOCK
= 50MHz
+25
C
74
70
77
dBFS
(3)
f
O
= 10MHz
f
CLOCK
= 50MHz
+25
C
71
64
73
dBFS
f
O
= 1MHz
f
CLOCK
= 100MHz
+25
C
72
70
75
dBFS
f
O
= 10MHz
f
CLOCK
= 100MHz
+25
C
68
66
70
dBFS
f
O
= 20MHz
f
CLOCK
= 100MHz
+25
C
61
58
62
dBFS
f
O
= 10MHz
f
CLOCK
= 200MHz
+25
C
66
66
70
dBFS
f
O
= 20MHz
f
CLOCK
= 200MHz
+25
C
58
62
67
dBFS
f
O
= 50MHz
f
CLOCK
= 200MHz
+25
C
52
50
55
dBFS
Output Noise
Bits 1-12 HIGH
+25
C
10.6
T
nV/
Hz
POWER SUPPLIES
Supply Voltages: V
EE
Full
4.5
5.2
5.5
T
T
T
V
Supply Currents: I
EEA
Pins 33 and 34
Full
30
46
60
T
T
T
mA
I
EED
Pins 5 and 55
Full
110
150
190
T
T
T
mA
Power Consumption
Operating
Full
900mW
1.3
T
T
W
TEMPERATURE RANGE
Specification: DAC600AN, BN
Ambient
Full
40
+85
T
T
C
JA
30
T
C/W
V
MEASURED
(FS) V
IDEAL
(FS)
X
100
V
IDEAL
(FS)
DAC600
3
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
V
EEA
............................................................................................ 0.3 to 7
V
EED
............................................................................................ 0.3 to 7
Logic Inputs ................................................................................ 0 to 5.5V
Reference Input Voltage .......................................................... 0 to +1.25V
Reference Input Current ......................................................... 0 to 1.56mA
Case Temperature .......................................................... 40
C to +125
C
Junction Temperature .................................................................... +150
C
Storage Temperature ...................................................... 55
C to +125
C
Lead Temperature (soldering, 10s) ................................................ +300
C
Stresses above these ratings may permanently damage the device.
TEMPERATURE
PRODUCT
DESCRIPTION
RANGE (AMBIENT)
DAC600AN, BN
68-Pin Plastic QUAD
40
C to +85
C
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER
(1)
DAC600AN, BN
68-Pin Plastic QUAD
312-1
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PIN #
DESIGNATION
DESCRIPTION
35
V
REF2
Analog Reference Voltage Center Tap
36
NC
37
NC
38
V
REF
Analog Reference Voltage
39
V
REF
Analog Reference Voltage
40
NC
41
NC
42
R
OFFSET
Offset Compensation
43
NC
44
BYPASS
0.1
F Bypass to Ground
45
NC
46
NC
47
ALTCOMPC
Control Amp PTAT Reference Compensation
(2)
48
AGND
Analog Signal Ground
49
NC
50
LBIAS
Ladder Bias Alternate Compensation
(2)
51
NC
52
NC
53
NC
54
Bit 1
MSB
55
DV
EE
Digital 5.2V Supply
56
DGND
Digital Signal Ground
57
DGND
Digital Signal Ground
58
Bit 2
59
Bit 3
60
Bit 4
61
NC
62
Bit 5
63
DGND
Digital Ground
64
Bit 6
65
Bit 7
66
DGND
Digital Ground
67
Bit 8
68
NC
PIN DEFINITIONS
PIN #
DESIGNATION
DESCRIPTION
1
BYPASS
Disables Latching of Data
2
CLK
CLOCK
3
CLKNOT
CLOCKNOT
4
DGND
Digital Ground
5
DV
EE
(1)
5.2V Supply
6
Bit 9
7
Bit 10
8
Bit 11
9
Bit 12
LSB
10
NC
11
NC
12
NC
13
V
OUT
DAC Output
14
V
OUT
DAC Output
15
LGND
Ladder Ground
16
LGND
Ladder Ground
17
V
OUTNOT
DAC Output Complement
18
V
OUTNOT
DAC Output Complement
19
NC
20
AGND
Analog Ground
21
NC
22
NC
23
NC
24
NC
25
NC
26
BYPASS
0.1
F Bypass to Ground
27
NC
28
ALTCOMPIB
PTAT-IB Reference Compensation
(2)
29
AGND
Analog Ground
30
AGND
Analog Ground
31
NC
32
LOOPCRNT
DAC Reference Alt. Loop Current
(Connect to AGND)
33
V
EE
(1)
5.2V Supply
34
V
EE
(1)
5.2V Supply
NC: no connect
NOTE: (1) Pins 5 and 55 typically draw 150mA of current. Pins 33 and 34 combined typically draw 46mA. (2) Connect bypass capacitor to V
EE
.
DAC600
4
Substrate Bias: Negative Supply V
CC
.
NC = Do not connect.
PAD
FUNCTION
1
Bypass
2
CLK
3
CLKNOT
4
DGND
5
DV
EE
6
Bit 9
7
NC
8
Bit 10
9
Bit 11
10
Bit 12
11
V
OUT
12
V
OUT
13
LGND
14
LGND
15
V
OUTNOT
16
V
OUTNOT
17
NC
18
AGND
19
NC
20
NC
21
NC
22
NC
23
NC
24
NC
25
NC
26
NC
27
ALTCOMPIB
28
AGND
29
AGND
30
NC
31
LOOPCRNT
32
AV
EE
33
AV
EE
34
V
REF2
35
NC
PAD
FUNCTION
36
NC
37
V
REF
38
V
REF
39
NC
40
NC
41
R
OFFSET
42
NC
43
NC
44
NC
45
NC
46
ALTCOMPC
47
AGND
48
NC
49
LBIAS
50
NC
51
NC
52
NC
53
Bit 1 (MSB)
54
DV
EE
55
DGND
56
DGND
57
Bit 2
58
Bit 3
59
Bit 4
60
NC
61
NC
62
NC
63
Bit 5
64
DGND
65
Bit 6
66
Bit 7
67
DGND
68
Bit 8
69
NC
DAC600 DIE TOPOGRAPHY
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
Die Size
160 x 140
5
4.06 x 3.56
0.13
Die Thickness
20
3
0.51
0.08
Min. Pad Size
4 x 4
0.10 x 0.10
Backing
Gold
Metallization
Gold
DICE INFORMATION
DAC600
5
DIFFERENTIAL NON-LINEARITY (40C)
Code
% of FSR
0
1000
3000
4000
0.012
0.0
0.012
0.024
2000
0.024
DIFFERENTIAL NON-LINEARITY (+85C)
Code
% of FSR
0
1000
3000
4000
0.012
0.0
0.012
0.024
2000
0.024
INTEGRAL NON-LINEARITY (40C)
Code
% of FSR
0
1000
3000
4000
0.024
0.0
0.024
0.048
2000
0.048
INTEGRAL NON-LINEARITY (+25C)
Code
% of FSR
0
1000
3000
4000
0.024
0.0
0.024
0.048
2000
0.048
INTEGRAL NON-LINEARITY (+85C)
Code
% of FSR
0
1000
3000
4000
0.024
0.0
0.024
0.048
2000
0.048
DIFFERENTIAL NON-LINEARITY (+25C)
Code
% of FSR
0
1000
3000
4000
0.012
0.0
0.012
0.024
2000
0.024
TYPICAL PERFORMANCE CURVES
At T
CASE
= +25
C, V
REF
= +1.0V, measured at V
OUT NOT
. Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth f
CLK
/2, unless
otherwise noted.
PDF 
ZIP