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Электронный компонент: DAC725KP

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Dual 16-Bit
DIGITAL-TO-ANALOG CONVERTER
DAC725
High
Byte
Low
Byte
D/A
Latch
8
8
16
16-
Bit
D/A
(A)
Control Logic
CLR
CS (A)
WR (A)
A
A
A
0
1
2
CS (B)
WR (B)
8-Bit
Data Bus
High
Byte
Low
Byte
D/A
Latch
8
8
16
16-
Bit
D/A
(B)
FEATURES
q
COMPLETE DUAL V
OUT
DAC
q
DOUBLE-BUFFERED INPUT REGISTER
q
HIGH-SPEED DATA INPUT:
Serial or Parallel
q
HIGH ACCURACY:
0.003% Linearity Error
q
14-BIT MONOTONICITY OVER
TEMPERATURE
q
PLASTIC PACKAGE
q
CLEAR INPUT TO SET ZERO OUTPUT
DESCRIPTION
The DAC725 is a dual 16-bit DAC, complete with
internal reference and output op amps. The DAC725 is
designed to interface to an 8-bit microprocessor bus,
but can also be interfaced to wider buses. The hybrid
construction minimizes the digital feedthrough typi-
cally associated with products that combine the digital
bus interface circuitry with high-accuracy analog cir-
cuitry.
The 16-bit data word is loaded into either of the DACs
in two 8-bit bytes per 16-bit word. The versatility of
the control lines allows the data word to be directed to
either DAC, in any order. The voltage-out DACs are
dedicated to a bipolar output voltage of
10V. The
output is immediately set to 0V when the Clear com-
mand is given. This feature, combined with the bus
interfacing and complete DAC circuitry, makes the
DAC725 ideal for automatic test equipment, power
control, servo systems, and robotics applications.
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1987 Burr-Brown Corporation
PDS-757D
Printed in U.S.A. August, 1993
2
DAC725
SPECIFICATIONS
ELECTRICAL
At T
A
= +25
C, V
CC
=
15V, and after a 10-minute warm-up unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC725JP
DAC725KP
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
INPUT
DIGITAL INPUT
Resolution
16
*
Bits
Bipolar Input Code
Binary Twos Complement
*
Logic Levels
(1)
: V
IH
+2
+5.5
*
*
V
V
IL
1
+0.8
*
*
V
I
IH
(V
I
= +2.7V)
1
*
A
I
IL
(V
I
= +0.4V)
1
*
A
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
0.003
0.006
0.0015
0.003
% of FSR
(2)
Differential Linearity Error
(3)
0.0045
0.012
0.003
0.006
% of FSR
At Bipolar Zero: KP
(3, 4)
0.003
0.006
% of FSR
Gain Error
(5)
0.07
0.2
*
0.15
%
Bipolar Zero Error
(5)
0.05
0.1
*
*
% of FSR
Montonicity Over Specified Temp. Range
13
14
Bits
Power Supply Sensitivity: +V
CC
, V
CC
0.0015
0.006
*
*
% of FSR/%V
CC
V
DD
0.0001
0.001
*
*
% of FSR/%V
DD
DRIFT (Over Specified Temperature Range)
Gain Drift
10
*
25
ppm/
C
Bipolar Zero Drift
5
*
12
ppm of FSR/
C
Differential Linearity Over Temperature
(3)
0.0045
0.012
0.003
0.006
% of FSR
Linearity Error Over Temperature
(3)
0.012
0.006
% of FSR
SETTLING TIME (to
0.003% of FSR)
(6)
20V Step (2k
load)
4
*
8
s
1LSB Step at Worst-Case Code
(7)
2.5
*
4
s
Slew Rate
10
*
V/
s
OUTPUT
Output Voltage Range
(8)
10
*
V
Output Current
5
*
mA
Output Impedance
0.15
*
Short Circuit to Common Duration
Indefinite
*
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
+11.4
+15
+16.5
*
*
*
V
V
CC
11.4
15
16.5
*
*
*
V
V
DD
+4.5
+5
+5.5
*
*
*
V
Current (No load,
15V supplies): +V
CC
+29
+35
*
*
mA
V
CC
35
40
*
*
mA
V
DD
+6
+10
*
*
mA
Power Dissipation (
15V supplies)
920
1175
*
*
mW
TEMPERATURE RANGE
Specification
0
+70
*
*
C
Storage
60
+150
*
*
C
*Specification same as model to the left.
NOTES: (1) Digital inputs are TTL, LSTTL, 54/74HC and 54/74HTC compatible over the specification temperature range. (2) FSR means Full-Scale Range. For
example, for
10V output, FSR = 20V. (3)
0.0015% of FSR is equal to 1LSB in 16-bit resolution.
0.003% of FSR is equal to 1LSB in 15-bit resolution.
0.006%
of FSR is equal to 1LSB in 14-bit resolution. (4) Error at input code 0000
H
(BTC). (5) Adjustable to zero with external trim potentiometer. Adjusting the gain
potentiometer rotates the transfer function around the bipolar zero point. (6) Maximum represents the 3
limit. Not tested for this parameter. (7) The bipolar worst-
case code change is FFFF
H
to 0000
H
(BTC). (8) Minimum supply voltage for
10V output swing is approximately
13V. Output swing for
12V supplies is at least
9V.
3
DAC725
ABSOLUTE MAXIMUM RATINGS
V
DD
to COMMON ........................................................................ 0V, +15V
+V
CC
to COMMON ...................................................................... 0V, +18V
V
CC
to COMMON ...................................................................... 0V, 18V
Digital Data Inputs to COMMON ...................................... 0.5V, V
DD
+ 0.5
DC Current any Input ......................................................................
10mA
Reference Out to COMMON ........................ Indefinite Short to COMMON
V
OUT
............................................................ Indefinite Short to COMMON
External Voltage Applied to R
F
.........................................................
18V
External Voltage Applied to D/A Output ...............................................
5V
Power Dissipation ........................................................................ 2000mW
Storage Temperature ...................................................... 60
C to +150
C
Lead Temperature (soldering, 10s) .................................................. 300
C
NOTE: These devices are sensitive to electrostatic discharge. Appropriate
I.C. handling procedures should be followed.
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. Exposure to absolute maximum condi-
tions for extended periods may affect device reliability.
CONNECTION DIAGRAM
High
Byte
Latch
Low
Byte
Latch
D/A
Latch
8
8
16
16-
Bit
D/A
GA (A)
SJ (A)
V
WR (A)
CS (A)
V
+V
CS (B)
WR (B)
GA (B)
SJ (B)
V
CLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DD
2
0
1
ACOM
(A)
CC
CC
ACOM
(B)
OUT
V
A
A
A
15
14
13
12
11
10
)
)
)
)
)
)
)
)
(D
(D
(D
(D
(D
(D
7
6
5
4
3
2
D
D
D
D
D
D
9
8
(D
(D
1
0
D
D
DCOM
High
Byte
Latch
Low
Byte
Latch
D/A
Latch
8
8
16
16-
Bit
D/A
OUT
(A)
(B)
PIN
DESIGNATOR
DESCRIPTION
1
CLR
Clear line. Sets the D/A
register to 0000
HEX
,
which gives bipolar zero
on the D/A output.
2
V
DD
Logic supply (+5V).
3
A
2
Latch enable for D/A latch
(active low).
4
A
0
Latch enable for "low byte"
input (active low).
5
A
1
Latch enable for "high byte"
input (active low).
6
D
7
(D
15
)
Input for data bit 7 if en-
(MSB)
abling low byte (LB) latch,
or data bit 15 if enabling
the high byte (HB) latch.
7
D
6
(D
14
)
Input for data bit 6 if en-
abling LB latch, or data bit
14 if enabling HB latch.
8
D
5
(D
13
)
Data bit 5 (LB) or data bit
13 (HB).
9
D
4
(D
12
)
Data bit 4 (LB) or data bit
12 (HB).
10
D
3
(D
11
)
Data bit 3 (LB) or data bit
11 (HB).
11
D
2
(D
10
)
Data bit 2 (LB) or data bit
10 (HB).
12
D
1
(D
9
)
Data bit 1 (LB) or data bit 9
(HB).
13
D
0
(D
8
)
Data bit 0 (LB) or data bit
8 (HB).
14
DCOM
Digital common.
15
V
OUT
(B)
Voltage output for DAC B.
16
ACOM (B)
Analog common for DAC B.
17
SJ (B)
Summing junction of the in-
ternal op amp for DAC B.
18
GA (B)
Gain adjust pin for DAC B.
19
WR (B)
Write control line for DAC B.
20
CS (B)
Chip select control line for
DAC B.
21
+V
CC
Positive supply voltage
(+15V).
22
V
CC
Negative supply voltage
(15V).
23
CS (A)
Chip select control line for
DAC A.
24
WR (A)
Write control line for DAC A.
25
V
OUT
(A)
Voltage output for DAC A.
26
ACOM (A)
Analog common for DAC A.
27
SJ (A)
Summing junction of the in-
ternal op amp for DAC A.
28
GA (A)
Gain adjust pin for DAC A.
PIN DESCRIPTIONS
ORDERING INFORMATION
LINEARITY ERROR
TEMPERATURE
MODEL
max (% of FSR)
RANGE
DAC725JP
0.012
0
C to +70
C
DAC725KP
0.006
0
C to +70
C
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
DAC725JP
28-Pin Plastic DIP
215
DAC725KP
28-Pin Plastic DIP
215
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
4
DAC725
DISCUSSION OF
SPECIFICATIONS
DIGITAL INPUT CODES
The DAC725 accepts positive-true binary twos complement
input code, as shown in Table I. The data is loaded into
either DAC, 8 bits at a time. The data may also be clocked
into the device in a serial format.
ANALOG OUTPUT
(Binary Two's Complement,
DIGITAL INPUT CODES
Bipolar Operation, All Models)
7FFF
H
+ Full Scale
0000
H
Zero
FFFF
H
1LSB
8000
H
Full Scale
TABLE I. Digital Input Codes.
ACCURACY
Linearity
This specification describes one of the most important mea-
sures of performance of a D/A converter. Linearity error is
the deviation of the analog output from a straight line drawn
through the end points (minus full-scale point and plus full-
scale point).
Differential Linearity Error
Differential Linearity Error (DLE) of a D/A converter is the
deviation from an ideal 1LSB change in the output when the
input changes from one adjacent code to the next. A differ-
ential linearity error specification of
1/2LSB means that the
output step size can be between 1/2LSB and 3/2LSB when
the input changes between adjacent codes. A negative DLE
specification of 1LSB maximum (0.006% for 14-bit reso-
lution) insures monotonicity.
Monotonicity
Monotonicity assures that the analog output will increase or
remain the same for increasing input digital codes. The
DAC725 is specified to be monotonic to 14 bits over the
entire specification range.
DRIFT
Gain Drift
Gain drift is a measure of the change in full-scale range
output over temperature expressed in parts per million per
degree centigrade (ppm/
C). Gain drift is established by:
(1) testing the end point differences at t
MIN
, +25
C and t
MAX
,
(2) calculating the gain error with respect to the +25
C
value, and
(3) dividing by the temperature change.
The DAC725 is specified for Maximum Gain and Offset
values at temperature. This tells the system designer the
maximum that can be expected over temperature, regardless
of room temperature values.
Zero Drift
Zero drift is a measure of change in the output with 0000
H
applied to the D/A converter inputs over the specified
temperature range. This code corresponds to 0V analog
output.
The maximum change in offset at t
MIN
or t
MAX
is referenced
to the zero error at +25
C and is divided by the temperature
change. This drift is expressed in FSR/
C.
SETTLING TIME
Settling time of the D/A is the total time required for the
analog output to settle within an error band around its final
value after a change in digital input. Refer to Figure 1 for
typical values for this family of products.
FIGURE 1. Final-Value Error Band Versus Full-Scale Range
Settling Time.
Settling times are specified to
0.003% of FSR (
1/2LSB
for 14 bits) for two input conditions: a full-scale range
change of 20V (
10V), and a 1LSB change at the "major
carry," the point at which the worst-case settling time
occurs. This is the worst-case point since all of the input bits
change when going from one code to the next.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
change in a power supply voltage on the D/A converter
output. It is defined as a percent of FSR change in the output
per percent of change in either the positive supply (+V
CC
),
negative supply (V
CC
) or logic supply (V
DD
) about the
nominal power supply voltages (see Figure 2). It is specified
for DC or low frequency changes. The typical performance
curve in Figure 2 shows the effect of high frequency changes
in power supply voltages.
0.1
Settling Time (s)
1
0.1
0.01
0.001
Final-Value Error Band % of
Full-Scale Range (% of FSR)
1
10
100
5
DAC725
Gain Adjustment
To adjust the gain of the DAC725, set the DAC to 7FFF
H
for
both DACs. Adjust the gain of each DAC to obtain the full
scale voltage of +9.99969V as shown in Table II.
FIGURE 2. Power Supply Rejection Versus Power Supply
Ripple Frequency.
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in the
Connection Diagram. 1
F to 10
F tantalum capacitors should
be located close to the D/A converter.
EXTERNAL ZERO AND GAIN ADJUSTMENT
Zero and gain may be trimmed by installing external zero
and gain potentiometers. Connect these potentiometers as
shown in the Connection Diagram and adjust as described
below. TCR of the potentiometers should be 100ppm/
C or
less. The 3.9M
and 270k
resistors (
20% carbon or
better) should be located close to the D/A converter to
prevent noise pickup. If it is not convenient to use these
high-value resistors, an equivalent "T" network, as shown in
Figure 3, may be substituted in place of the 3.9M
resistor.
A 0.001
F to 0.01
F low-leakage film capacitor should be
connected from Gain Adjust to Analog Common to prevent
noise pickup. Refer to Figure 4 for relationship of Offset and
Gain adjustments.
FIGURE 3. Equivalent Resistances.
180k
180k
3.9M
10k
Zero Adjustment
By loading the code 0000
H
, the DAC will force 0V. Offset
is adjusted by using the circuit of Figure 5. An alternate
method would be to use the CLR control to set the DAC to
0V. Zero calibration should be made before gain calibration.
BIPOLAR OUTPUT,
10V
DIGITAL
INPUT
CODE
16 Bits
15 Bits
14 Bits
UNITS
One LSB
305
610
1224
V
7FFF
H
+9.99969
+9.99939
+9.99878
V
8000
H
10
10
10
V
TABLE II. Digital Input Codes.
INTERFACE LOGIC AND TIMING
The control logic functions are chip select (CS
A
or CS
B
),
write (WR
A
or WR
B
), latch enable (A
0
, A
1
, A
2
), and clear
(CLR). These pins provide the control functions for the micro-
processor interface. There is a write and a chip select for both
DAC
A
and for DAC
B
channels. This allows the 8-bit data
word to be latched from the data bus to the input latch or
from the input latch to the DAC latch, of DAC
A
, DAC
B
, or
both.
A
0
A
1
A
2
WR (A)
CS (A)
DESCRIPTION
1
1
0
0
0
DAC latch enabled, Channel A
1
0
1
0
0
Input latch high byte enabled, Channel A
1
0
0
0
0
High byte flows through to DAC, Channel A
0
1
1
0
0
Low byte latched from data bus, Channel A
0
1
0
0
0
Low byte flows through to DAC, Channel A
0
0
1
1
1
Serial input mode for byte latches
X
X
X
1
0
No data is latched
X
X
X
0
1
No data is latched
"1" or "0" indicates TTL Logic Level Channel A shown.
TABLE III. Truth Table of Data Transfers.
FIGURE 4. Relationship of Zero and Gain Adjustments
for the DAC725.
Range of
Gain Adjust
Offset Adjust
Translates
the Line
Range and
Offset Adjust
1LSB
+ Full Scale
Input = 8000
Analog Output
H
Input = 7FFF
H
Input = 0000
H
Full Scale
Digital Input
Full Scale Range
Gain
Adjust
Rotates
the Line
1
Power Supply Ripple Frequency (Hz)
10
100
1k
10k
100k
0.03
0.025
0.02
0.015
0.01
0.005
0
% of FSR Error Per % of Change in V
SUPPLY
15V Supply
+15V Supply
+5V Supply
6
DAC725
The latch enable lines control which latch is being loaded.
Line A
1
in combination with WR and CS enables the high
byte of the DAC channel to be latched through the byte latch.
The A
0
line, in conjunction with the WR and CS, latches the
data for the low byte. When A
2
, CS, and WR are low at the
same time, the data is latched through the D/A latch and the
DAC changes output voltage. Each latch may be made
transparent by maintaining its enable signal at logic "0".
The serial data mode is activated when both A
0
and A
1
are
at logic low simultaneously. The data (MSB first) is clocked
in to pin 13 with clock pulses on the WR pin. The data is
then latched through to the DAC as a complete 16-bit word
selected by A
2
.
The CLR line resets both input latches to all zeros and sets
the DAC latch to 0000
H
. This is the binary code that gives
a null, or zero, at the output of the DAC.
The maximum clock rate of the latches is 10MHz. The
minimum time between the write (WR) pulses for succes-
sive enables is 20ns. In the serial input mode, the maximum
rate at which data can be clocked into the input shift register
is 10MHz. The timing of the control signals is given in
Figure 6.
OVER TEMP.
INTERVAL
DESCRIPTION
ns, min
ns, max
t
DW
Data valid to end of WR
80
t
CW
CS valid to end of WR
80
t
AW
A
0
, A
1
, A
2
valid to end of WR
80
t
WP
Write pulse width
80
t
DH
Data hold after end of WR
0
FIGURE 6. Logic Timing Diagram.
FIGURE 5. Connections for Gain and Offset Adjust.
t
CW
t
AW
t
DW
t
DH
t
WP
CS
0
A
1
, A
2
, A
D0D15, SI
WR
High
Byte
Latch
Low
Byte
Latch
D/A
Latch
8
8
16
16-
Bit
D/A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
High
Byte
Latch
Low
Byte
Latch
D/A
Latch
8
8
16
16-
Bit
D/A
270k
0.0022F
Gain
Adjust (A)
+V
CC
V
CC
+V
CC
3.9M
Offset
Adjust (A)
*
*
270k
0.0022F
Gain
Adjust (B)
+V
CC
V
CC
+V
CC
3.9M
Offset
Adjust (B)
*
*
* 10k
to 100k
7
DAC725
INSTALLATION
Because of the extremely high accuracy of the D/A
converter, system design problems such as grounding and
contact resistance become very important. For a 16-bit
converter with a +10V full-scale range, 1LSB is 153
V.
With a load current of 5mA, series wiring and connector
resistance of only 30m
will cause the output to be in error
by 1LSB. To understand what this means in terms of a
system layout, the resistance of typical 1oz copper-clad
printed circuit board material is approximately 1/2m
per
square mil. In the example above, a 10mil-wide conductor
60mil long would cause a 1LSB error in R
2
and R
3
of Figure
7.
In Figure 7, lead and contact resistances are represented as
R
2
through R
6
. As long as the load resistance (R
L
) remains
constant, the resistances of R
2
and R
3
will appear as gain
errors when the output is sensed across the load. If the output
is sensed at the DAC725 output terminal and the system
analog common, R
2
and R
3
appear in series with R
L
. R
4
has
a current through it that varies by only 1% of the nominal
2mA current for all code combinations. This IR drop causes
an offset error, and is calibrated out as an offset error.
The current through the digital common varies directly with
the digital code that is loaded into the DAC. The current is
not the same for each code. If this IR drop is allowed to
modulate the analog common, there may be code-dependent
errors in the analog output.
The IR drop across R
6
may cause accuracy problems if the
analog commons of several circuits are "daisy chained"
along the power supply analog common. All analog sense
lines should be referenced to the system analog common.
APPLICATIONS
WAVEFORM GENERATION
The DAC725 has attributes that make it ideal for very low
distortion waveform synthesis. Due to special design tech-
niques, the feedthrough energy is much lower than that
found in other D/A converters available today. In addition to
the low feedthrough glitch energy, the input logic will
operate with data rates of 10MHz. This makes the DAC725
ideal for waveform synthesis.
PROGRAMMABLE POWER SUPPLIES
The DAC725 is an excellent choice for programmable
power supply applications. The DAC outputs may be pro-
grammed to track or oppose each other. If the load is
floating, and can be driven differentially, the dynamic range
will be 17 bits, because the full-scale range doubles for the
same sized LSB. The clear line (CLR) sets both DAC
outputs to zero, and would be used at power-up to bring the
system up in a safe state. The CLR line could also be used
if an over-power state is sensed.
ISOLATION
The DAC725 can accept serial input data, which means that
only six optoisolators are needed for two DACs. The data is
clocked into the input latch using the WR pin. The 16-bit
data word is latched into the DAC selected by A
2
. When A
0
and A
1
are simultaneously low, the serial mode is enabled.
High
Byte
Low
Byte
D/A
Latch
8
8
16
16-
Bit
D/A
(A)
8-Bit
Data Bus
High
Byte
Low
Byte
D/A
Latch
8
8
16
16-
Bit
D/A
(B)
2mA
Constant
2mA
Constant
0 to 2mA
Typ
0 to 2mA
Typ
0 to 4mA Typ
Analog Common B
Analog Common A
Digital Common
Out A
Out B
System Analog
Common
R
L
V
Supply
CC
V
Supply
DD
+V
CC
V
CC
+V
DD
R
6
R
2
Digital
Common
Analog
Common
R
4
R
5
R
3
FIGURE 7. System Wiring Example.