16-Bit, Dual Voltage Output
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The DAC7632 is a 16-bit, dual channel, voltage output,
Digital-to-Analog Converter (DAC) which provides 15-bit
monotonic performance over the specified temperature range.
The device accepts 24-bit serial input data, has double-
buffered DAC input logic (allowing simultaneous update of
both DACs), and provides a serial data output for daisy-
chaining multiple devices. A programmable asynchronous
reset clears all registers to a mid-scale code of 8000
H
or to
a zero-scale code of 0000
H
. The DAC7632 can operate from
a single +5V supply or from +5V and 5V supplies, providing
an output range of 0V to +2.5V or 2.5V to +2.5V, respec-
tively.
Low power and small size per DAC make the DAC7632
ideal for industrial process control, data acquisition sys-
tems, and closed-loop servo-control. The DAC7632 is avail-
able in an LQFP-32 package and specified over a 40
C to
+85
C temperature range.
FEATURES
q
LOW POWER: 4mW
q
UNIPOLAR OR BIPOLAR OPERATION
q
SETTLING TIME: 10
s to
0.003% FSR
q
15-BIT LINEARITY AND MONOTONICITY:
40
C to +85
C
q
PROGRAMMABLE RESET TO MID-SCALE
OR ZERO-SCALE
q
DOUBLE-BUFFERED DATA INPUTS
APPLICATIONS
q
PROCESS CONTROL
q
CLOSED-LOOP SERVO-CONTROL
q
MOTOR CONTROL
q
DATA ACQUISITION SYSTEMS
q
DAC-PER-PIN PROGRAMMERS
DAC7632
SBAS234 FEBRUARY 2002
www.ti.com
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DAC A
DAC
Register A
Input
Register A
Shift
Register
DAC B
DAC
Register B
Input
Register B
V
REF
L
V
REF
H
V
REF
H
Sense
V
REF
L
Sense
V
OUT
B
V
OUT
A
V
OUT
B
Sense
SDI
SDO
Control
Logic
CS
CLK
RST
RSTSEL
LDAC
LOAD
AGND
DGND
V
OUT
A
Sense
V
CC
V
SS
V
DD
DAC7632
DAC763
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DAC7632
2
SBAS234
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ABSOLUTE MAXIMUM RATINGS
(1)
V
CC
and V
DD
to V
SS
.............................................................. 0.3V to 11V
V
CC
and V
DD
to GND ........................................................... 0.3V to 5.5V
V
REF
L
to V
SS
............................................................. 0.3V to (V
CC
V
SS
)
V
CC
to V
REF
H ............................................................ 0.3V to (V
CC
V
SS
)
V
REF
H
to V
REF
L ......................................................... 0.3V to (V
CC
V
SS
)
Digital Input Voltage to GND ................................... 0.3V to V
DD
+ 0.3V
Digital Output Voltage to GND ................................. 0.3V to V
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150
C
Operating Temperature Range ........................................ 40
C to +85
C
Storage Temperature Range ......................................... 65
C to +125
C
Lead Temperature (soldering, 10s) ............................................... +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
MONOTONICITY
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
DAC7632VF
14 Bits
LQFP-32
VF
40
C to +85
C
DAC7632
DAC7632VFT
Tape and Reel, 250
"
"
"
"
"
"
DAC7632VFR
Tape and Reel, 1000
DAC7632VFB
15 Bits
LQFP-32
VF
40
C to +85
C
DAC7632B
DAC7632VFB T
Tape and Reel, 250
"
"
"
"
"
"
DAC7632VFB R
Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
DAC7632
3
SBAS234
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DAC7632VF
DAC7632VFB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error
3
4
2
3
LSB
Linearity Match
4
2
LSB
Differential Linearity Error
2
3
1
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Bipolar Zero Error
1
3
mV
Bipolar Zero Error Drift
5
10
ppm/
C
Full-Scale Error
1
3
mV
Full-Scale Error Drift
5
10
ppm/
C
Bipolar Zero Matching
Channel-to-Channel Matching
1
3
mV
Full-Scale Matching
Channel-to-Channel Matching
1
3
mV
Power-Supply Rejection Ratio (PSRR)
At Full Scale
10
100
ppm/V
ANALOG OUTPUT
Voltage Output
R
L
= 10k
V
REF
L
V
REF
H
V
Output Current
1.25
+1.25
mA
Maximum Load Capacitance
No Oscillation
500
pF
Short-Circuit Current
10, +30
mA
Short-Circuit Duration
GND or V
CC
or V
SS
Indefinite
REFERENCE INPUT
Ref High Input Voltage Range
V
REF
L + 1.25
+2.5
V
Ref Low Input Voltage Range
2.5
V
REF
H 1.25
V
Ref High Input Current
500
A
Ref Low Input Current
500
A
DYNAMIC PERFORMANCE
Settling Time
To
0.003%, 5V Output Step
8
10
s
Channel-to-Channel Crosstalk
0.5
LSB
Digital Feedthrough
2
nV-s
Output Noise Voltage
f = 10kHz
60
nV/
Hz
DAC Glitch
7FFF
H
to 8000
H
or 8000
H
to 7FFF
H
40
nV-s
DIGITAL INPUT
V
IH
0.7 V
DD
V
V
IL
0.3 V
DD
V
I
IH
10
A
I
IL
10
A
DIGITAL OUTPUT
V
OH
I
OH
= 0.8mA
3.6
4.5
V
V
OL
I
OL
= 1.6mA
0.3
0.4
V
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
V
V
CC
+4.75
+5.0
+5.25
V
V
SS
5.25
5.0
4.75
V
I
CC
0.7
1.1
mA
I
DD
50
A
I
SS
1.2
0.8
mA
Power
7.5
11.5
mW
TEMPERATURE RANGE
Specified Performance
40
+85
C
Specifications same as DAC7632VF.
ELECTRICAL CHARACTERISTICS
(Dual Supply)
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REF
H = +2.5V, and V
REF
L = 2.5V, unless otherwise noted.
DAC7632
4
SBAS234
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DAC7632VF
DAC7632VFB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ACCURACY
Linearity Error
(1)
3
4
2
3
LSB
Linearity Match
4
2
LSB
Differential Linearity Error
2
3
1
2
LSB
Monotonicity, T
MIN
to T
MAX
14
15
Bits
Zero Scale Error
1
3
mV
Zero Scale Error Drift
5
10
ppm/
C
Full-Scale Error
1
3
mV
Full-Scale Error Drift
5
10
ppm/
C
Zero Scale Matching
Channel-to-Channel Matching
1
3
mV
Full-Scale Matching
Channel-to-Channel Matching
1
3
mV
Power Supply Rejection Ratio (PSRR)
At Full Scale
10
100
ppm/V
ANALOG OUTPUT
Voltage Output
R
L
= 10k
0
V
REF
H
V
Output Current
1.25
+1.25
mA
Maximum Load Capacitance
No Oscillation
500
pF
Short-Circuit Current
10, +30
mA
Short-Circuit Duration
GND or V
CC
Indefinite
REFERENCE INPUT
Ref High Input Voltage Range
V
REF
L + 1.25
+2.5
V
Ref Low Input Voltage Range
2.5
V
REF
H 1.25
V
Ref High Input Current
250
A
Ref Low Input Current
250
A
DYNAMIC PERFORMANCE
Settling Time
To
0.003%, 5V Output Step
8
10
s
Channel-to-Channel Crosstalk
0.5
LSB
Digital Feedthrough
2
nV-s
Output Noise Voltage, f = 10kHz
60
nV/
Hz
DAC Glitch
7FFF
H
to 8000
H
or 8000
H
to 7FFF
H
40
nV-s
DIGITAL INPUT
V
IH
0.7 V
DD
V
V
IL
0.3 V
DD
V
I
IH
10
A
I
IL
10
A
DIGITAL OUTPUT
V
OH
I
OH
= 0.8mA
3.6
4.5
V
V
OL
I
OL
= 1.6mA
0.3
0.4
V
POWER SUPPLY
V
DD
+4.75
+5.0
+5.25
V
V
CC
+4.75
+5.0
+5.25
V
V
SS
0
0
0
V
I
CC
0.5
0.9
mA
I
DD
50
A
Power
2.5
4.5
mW
TEMPERATURE RANGE
Specified Performance
40
+85
C
Specifications same as DAC7632VF.
NOTE: (1) If V
SS
= 0V, the specification applies to Code 0040
H
and above due to possible negative zero-scale error.
SPECIFICATIONS
(Dual Supply)
At T
A
= T
MIN
to T
MAX
, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REF
H = +2.5V, and V
REF
L = 0V, unless otherwise noted.
DAC7632
5
SBAS234
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PIN
NAME
DESCRIPTION
1
V
CC
Analog +5V Power Supply
2, 3
AGND
Analog Ground
4
NC
No Connection
5, 6
DGND
Digital Ground
7
V
DD
Digital +5V Power Supply
8
SDO
Serial Data Output
9-16
NC
No Connection
17
CLK
Data Clock Input
18
SDI
Serial Data Input
19
CS
Chip Select, Active LOW
20
RSTSEL
Reset Select. Determines the action of RST. If
HIGH, a RST common will set the DAC registers
to mid-scale code (8000
H
). If LOW, a RST
command will set the DAC registers to zero-scale
code (0000
H
).
21
RST
Reset, Rising Edge Triggered. Depending on the
state of RSTSEL, the DAC registers are set to
either mid-scale code or zero-scale code.
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
22
LDAC
DAC Register Load Control, Rising Edge
Triggered
23
LOAD
DAC Input Register Load Control, Active LOW
24
V
SS
Analog 5V Power Supply (or 0V for Single Supply)
25
V
OUT
B
DAC B Output Voltage
26
V
OUT
B Sense
DAC B Output Amplifier Inverting Input. Used to
close the feedback loop at the load.
27
V
REF
H Sense
DAC A and B Reference High Sense Input
28
V
REF
H
DAC A and B Reference High Input
29
V
REF
L
DAC A and B Reference Low Input
30
V
REF
L Sense
DAC A and B Reference Low Sense Input
31
V
REF
A Sense
DAC A Output Amplifier Inverting Input. Used to
close the feedback loop at the load.
32
V
OUT
A
DAC A Output Voltage
Top View
SSOP
PIN CONFIGURATION
V
CC
AGND
AGND
NC
DGND
DGND
V
DD
SDO
V
SS
LOAD
LDAC
RST
RSTSEL
CS
SDI
CLK
1
2
3
4
5
6
7
8
NC = No Connection
24
23
22
21
20
19
18
17
DAC7632
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
NC
NC
NC
NC
NC
NC
NC
NC
9
10
11
12
13
14
15
16
DAC7632
6
SBAS234
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40
C
TYPICAL CHARACTERISTICS: V
SS
= 0V
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
+25
C
+85
C
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7632
7
SBAS234
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TYPICAL CHARACTERISTICS: V
SS
= 0V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
REF
H CURRENT vs CODE
(all DACs sent to indicated code)
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.00
0.05
0.10
0.15
0.20
0.25
0.30
V
REF
L CURRENT vs CODE
(all DACs sent to indicated code)
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
1
0.8
0.6
0.4
0.2
0
ANALOG SUPPLY CURRENT vs TEMPERATURE
I
CC
(mA)
Temperature (
C)
40
15
10
35
60
85
Data = FFFF
H
(all DACs)
No Load
1.0
0.8
0.6
0.4
0.2
0.0
Digital Input Code
0000
H
2000
H
4000
H
6000
H
8000
H
A000
H
C000
H
E000
H
FFFF
H
ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE
I
CC
(mA)
All DACs
No Load
DAC B
DAC A
3
2
1
0
1
2
3
Temperature (
C)
40
15
85
10
35
60
ZERO-SCALE ERROR vs TEMPERATURE
Zero-Scale Error (mV)
Code (0040
H
)
FULL-SCALE ERROR vs TEMPERATURE
Full-Scale Error (mV)
DAC B
DAC A
3
2
1
0
1
2
3
Temperature (
C)
40
15
85
10
35
60
Code (FFFF
H
)
DAC7632
8
SBAS234
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BROADBAND NOISE
Time (10
s/div)
Noise Voltage (50
V/div)
BW = 10kHz
Code = 8000
H
TYPICAL CHARACTERISTICS: V
SS
= 0V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
1000
100
10
Frequency (Hz)
10
100
1000
10000
100000
1000000
OUTPUT NOISE VOLTAGE vs FREQUENCY
Noise (nV/
Hz)
Time (1
s/div)
OUTPUT VOLTAGE
vs MID-SCALE GLITCH PERFORMANCE
Output Voltage (20mV/div)
+5V
LDAC
0
7FFF
H
to 8000
H
Time (1
s/div)
OUTPUT VOLTAGE
vs MID-SCALE GLITCH PERFORMANCE
Output Voltage (20mV/div)
+5V
LDAC
0
8000
H
to 7FFF
H
+5V
LDAC
0
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +2.5V)
Output Voltage
Large-Signal Settling Time: 1V/div
Small-Signal Settling Time: 500
V/div
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2mV)
Output Voltage
+5V
LDAC
0
Large-Signal Settling Time: 1V/div
Small-Signal Settling
Time: 500
V/div
DAC7632
9
SBAS234
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TYPICAL CHARACTERISTICS: V
SS
= 0V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 0V, V
REFH
= +2.5V, V
REFL
= 0V, representative unit, unless otherwise specified.
V
SS
= 5V
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
+85
C
+25
C
0.50
0.40
0.30
0.20
0.10
0.00
Logic Input Level for Digital Inputs (V)
0
1
2
3
4
5
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS
Logic Supply Current (mA)
Typical of One
Digital Input
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
5
4
3
2
1
0
R
LOAD
(k
)
0.01
0.1
1
10
100
V
OUT
vs R
LOAD
V
OUT
(V)
Source
Sink
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7632
10
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40
C
TYPICAL CHARACTERISTICS: V
SS
= 5V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, 40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, 40
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
+0.6
+0.5
+0.4
+0.3
+0.2
+0.1
0.0
V
REF
H CURRENT vs CODE
(all DACs sent to indicated code)
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V
REF
L CURRENT vs CODE
(all DACs sent to indicated code)
V
REF
Current (mA)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
BIPOLAR ZERO ERROR vs TEMPERATURE
Bipolar Zero Error (mV)
DAC B
DAC A
3
2
1
0
1
2
3
Temperature (
C)
40
15
85
10
35
60
Code (8000
H
)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
Positive Full-Scale Error (mV)
DAC B
DAC A
3
2
1
0
1
2
3
Temperature (
C)
40
15
85
10
35
60
Code (FFFF
H
)
DAC7632
11
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TYPICAL CHARACTERISTICS: V
SS
= 5V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
Negative Full-Scale Error (mV)
DAC A
DAC B
3
2
1
0
1
2
3
Temperature (
C)
40
15
85
10
35
60
Code (0000
H
)
5
4
3
2
1
0
1
2
3
4
5
R
LOAD
(k
)
0.01
0.1
1
10
100
V
OUT
vs R
LOAD
V
OUT
(V)
Source
Sink
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(2.5V to +2.5V)
Output Voltage
+5V
LDAC
0
Large-Signal Settling Time: 2V/div
Small-Signal Settling Time: 500
V/div
Time (2
s/div)
OUTPUT VOLTAGE vs SETTLING TIME
(+2.5V to 2.5V)
Output Voltage
+5V
LDAC
0
Large-Signal Settling Time: 2V/div
Small-Signal Settling Time:
500
V/div
1.00
0.75
0.50
0.25
0.00
0.25
0.50
0.75
1.00
ANALOG SUPPLY CURRENT vs DIGITAL INPUT CODE
Analog Supply Current (mA)
0000
H
2000
H
4000
H
I
CC
I
SS
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
No Load
1
0.5
0
0.5
1
1.5
ANALOG SUPPLY CURRENT vs TEMPERATURE
Analog Supply Current (mA)
I
SS
I
CC
Data = FFFF
H
(all DACs)
No Load
Temperature (
C)
40
15
10
35
60
85
DAC7632
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FIGURE 1. DAC7632 Architecture.
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
V
REF
H
V
OUT
V
OUT
Sense
V
REF
H Sense
V
REF
L
V
REF
L Sense
R
F
TYPICAL CHARACTERISTICS: V
SS
= 5V
(Cont.)
At T
A
= +25
C, V
DD
= V
CC
= +5V, V
SS
= 5V, V
REFH
= +2.5V, V
REFL
= 2.5V, representative unit, unless otherwise specified.
Time (1
s/div)
OUTPUT VOLTAGE
vs MID-SCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
7FFF
H
to 8000
H
Time (1
s/div)
OUTPUT VOLTAGE
vs MID-SCALE GLITCH PERFORMANCE
Output Voltage (50mV/div)
+5V
LDAC
0
8000
H
to 7FFF
H
THEORY OF OPERATION
The DAC7632 is a dual channel, voltage output, 16-bit DAC.
The architecture is an R-2R ladder configuration with the
three MSB's segmented, followed by an operational amplifier
that serves as a buffer. Each DAC has its own R-2R ladder
network, segmented MSBs, and output op amp, as shown in
Figure 1. The minimum voltage output (zero-scale) and
maximum voltage output (full-scale) are set by the external
voltage references V
REF
L and V
REF
H, respectively.
The digital input is a 24-bit serial word that contains an
address bit for selecting one of two DACs, a quick load bit,
six unused bits, and the 16-bit DAC code (MSB first). The
converters can be powered from either a single +5V supply
or a dual
5V supply. The device offers a reset function
which immediately sets all DAC output voltages, DAC regis-
ters and input registers to mid-scale (code 8000
H
) or to zero-
scale (code 0000
H
), depending on the state of RSTSEL. See
Figures 2 and 3 for the basic configurations of the DAC7632.
DAC7632
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FIGURE 2. Basic Single-Supply Operation of the DAC7632.
V
CC
AGND
AGND
NC
DGND
DGND
V
DD
SDO
V
SS
LOAD
LDAC
RST
RSTSEL
CS
SDI
CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DAC7632
9
10
11
12
13
14
15
16
NC
NC = No Connection
NC
NC
NC
NC
NC
NC
NC
CLOCK
32
0.1
F
31
30
29
28
+2.5V
27
26
25
V
OUTA
V
OUTA
Sense
V
REFL
Sense
V
REFL
V
REFH
V
REFH
Sense
V
OUTB
Sense
V
OUTB
SERIAL DATA IN
CHIP SELECT
RESET INPUT AND DAC REGISTERS
LOAD DAC REGISTERS
LOAD INPUT REGISTER(S)
0V to +2.5V
0V to +2.5V
+5V
1
F
0.1
F
+5V
1
F
FIGURE 3. Basic Dual-Supply Operation of the DAC7632.
24
23
22
21
20
19
18
17
0.1
F
1
F
5V
+5V
V
CC
AGND
AGND
NC
DGND
DGND
V
DD
SDO
V
SS
LOAD
LDAC
RST
RSTSEL
CS
SDI
CLK
1
2
3
4
5
6
7
8
DAC7632
9
10
11
12
13
14
15
16
NC
NC = No Connection.
NC
NC
NC
NC
NC
NC
NC
CLOCK
32
0.1
F
31
30
29
28
+2.5V
27
26
25
V
OUTA
V
OUTA
Sense
V
REFL
Sense
V
REFL
V
REFH
V
REFH
Sense
V
OUTB
Sense
V
OUTB
SERIAL DATA IN
CHIP SELECT
RESET INPUT AND DAC REGISTERS
LOAD DAC REGISTERS
LOAD INPUT REGISTER(S)
2.5V to
+2.5V
2.5V
2.5V to
+2.5V
+5V
1
F
0.1
F
+5V
1
F
DAC7632
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FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual-Supply Performance.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
1000pF
V
OUT
V
OUT
100
100
+2.5V
+V
2.5V
V
V
+V
OPA2234
2200pF
1000pF
2200pF
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
R
W2
R
W1
+2.5V
+V
V
OUT
R
W1
R
W2
V
OUT
FIGURE 4. Analog Output Closed-Loop Configuration
R
W
represents wiring resistances.
ANALOG OUTPUTS
When V
SS
= 5V (dual-supply operation), the output amplifier
can swing to within 2.25V of the supply rails over the 40
C
to +85
C temperature range. When V
SS
= 0V (single-supply
operation), and with R
LOAD
also connected to ground, the
output can swing to ground. Care must also be taken when
measuring the zero-scale error when V
SS
= 0V. Since the
output cannot swing below ground, the output voltage may
not change for the first few digital input codes (0000
H
, 0001
H
,
0002
H
, etc.) if the output amplifier has a negative offset. At
the negative limit of 2mV, the first specified output starts at
code 0040
H
.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 2.5V full-scale range
has a 1LSB value of 38
V. With a load current of 1mA, series
wiring and connector resistance of only 40m
(R
W2
) will
cause a voltage drop of 40
V, as shown in Figure 4. To
understand what this means in terms of a system layout, the
resistivity of a typical 1 ounce copper-clad printed circuit
board is 1/2m
per square. For a 1mA load, a 10 milli-inch
wide printed circuit conductor 600 milli-inches long will result
in a voltage drop of 30
V.
The DAC7632 offers a force and sense output configuration
for the high open-loop gain output amplifier. This feature
allows the loop around the output amplifier to be closed at the
load, as shown in Figure 4, thus ensuring an accurate output
voltage.
REFERENCE INPUTS
The reference inputs, V
REF
L and V
REF
H, can be any voltage
between V
SS
+ 2.5V and V
CC
2.5V, provided that V
REF
H is
at least 1.25V greater than V
REF
L. The minimum output of
each DAC is equal to V
REF
L
plus a small offset voltage
(essentially, the offset of the output op amp). The maximum
output is equal to V
REF
H plus a similar offset voltage. Note
that V
SS
(the negative power supply) must either be
connected to ground or must be in the range of 4.75V to
5.25V. The voltage on V
SS
sets several bias points within
the converter. If V
SS
is not in one of these two configurations,
the bias values may be in error and proper operation of the
device may be affected.
The current into the V
REF
H input and out of V
REF
L depends
on the DAC output voltages, and can vary from a few
microamps to approximately 0.5mA. The reference input
appears as a varying load to the reference supply. If the
reference applied can sink or source the required current, a
reference buffer is not required. The DAC7632 features
reference drive and sense connections such that the internal
errors caused by the changing reference current and the
circuit impedances can be minimized. Figures 5 through 13
show different reference configurations and the effect on the
integral linearity and differential linearity, for each case.
DAC7632
15
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FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
1000pF
V
OUT
V
OUT
100
+2.5V
2k
98k
+0.050V
+V
+V
OPA2350
2200pF
1000pF
2200pF
100
FIGURE 9. Single-Supply Buffered Reference with V
REF
L = +1.25V and V
REF
H = +2.5V.
FIGURE 7. Integral Linearity and Differential Linearity Error
Characteristic Curves for Figure 6.
FIGURE 8. Integral Linearity and Differential Linearity Error
Characteristic Curves for Figure 9.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
1000pF
V
OUT
V
OUT
100
+V
OPA2350
2200pF
1000pF
2200pF
+2.5V
+V
+V
+1.25V
100
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
DAC7632
16
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FIGURE 11. Linearity and Differential Linearity Error Charac-
teristic Curves for Figure 10.
FIGURE 12. Low-Cost Single-Supply Configuration.
FIGURE 13. Linearity and Differential Linearity Error Charac-
teristic Curves for Figure 12.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
V
OUT
V
OUT
+2.5V
+V
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
LE (LSB)
DLE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
C)
0000
H
2000
H
4000
H
6000
H
8000
H
Digital Input Code
A000
H
C000
H
E000
H
FFFF
H
FIGURE 10. Single-Supply Buffered V
REF
H.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
V
OUT
V
OUT
+V
OPA2350
+2.5V
+V
1000pF
100
2200pF
DIGITAL INTERFACE
See Table I for the basic control logic for the DAC7632. The
interface consists of a Serial Data Clock (CLK) input, Serial
Data Input (SDI), Input Register Load Control Signal (LOAD),
and DAC Register Load Control Signal (LDAC). In addition, a
Chip Select (CS ) input is available to enable serial communi-
cation when there are multiple serial devices attached to a
single serial bus. An asynchronous Reset (RST) input (rising
edge triggered) is provided to simplify start-up conditions,
periodic resets, or emergency resets to a known state, de-
pending on the status of the Reset Select (RSTSEL) signal.
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Figure 15). The first bit
(DACSEL) selects the input register that will be updated
when LOAD goes LOW. The third bit is a "Quick Load" bit
such that if HIGH, the code in the shift register is loaded into
both input registers when the LOAD signal goes LOW. If the
"Quick Load" bit is LOW when an active LOAD signal is
issued, the content of the shift register is loaded only to the
input register that is addressed by DACSEL. The "Quick
Load" bit is followed by five unused bits. The last 16 bits
(MSB first) make up the DAC code.
DAC7632
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INPUT
DAC
DACSEL
CS
RST
RSTSEL
LDAC
LOAD
REGISTER
REGISTER
MODE
DAC
0
L
H
X
X
L
Write
Hold
Write Input
A
1
L
H
X
X
L
Write
Hold
Write Input
B
X
H
H
X
H
Hold
Write
Update
All
X
H
H
X
H
H
Hold
Hold
Hold
All
X
X
L
X
X
Reset to 0000
H
Reset to 0000
H
Reset to Zero-Scale
All
X
X
H
X
X
Reset to 8000
H
Reset to 8000
H
Reset to Mid-scale
All
TABLE I. DAC7632 Logic Truth Table.
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
DACSEL
X
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
QUICK
LOAD
SERIAL DATA INPUT
CS
(1)
CLK
(1)
LOAD
RST
SERIAL SHIFT REGISTER
H
(2)
X
(3)
H
H
No Change
L
(4)
L
H
H
No Change
L
(5)
H
H
Advanced One Bit
L
H
H
Advanced One Bit
H
(6)
X
L
(7)
H
No Change
H
(6)
X
H
(8)
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don't Care. (4) L = Logic LOW. (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a "false clock" from
advancing the shift register and changing the shift register. (7) If data is
clocked into the serial register while LOAD is LOW, the input registers will
change as data flows through the shift register. This will corrupt the data
in each DAC register that has been erroneously selected. (8) Rising edge
of RST causes no change in the contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
FIGURE 14. Daisy-Chaining Multiple DAC7632s.
DAC7632
CLK
SDI
CS
SCK
DIN
CS
SDO
DAC7632
CLK
SDI
CS
SDO
DAC7632
CLK
SDI
CS
SDO
To
Other
Serial
Devices
Data presented to SDI is clocked into the shift register on
each rising CLK edge. This data is latched into the input
register(s) via a logic-low level on LOAD. The data is directed
from the shift register to the desired input register(s) specified
by data bits 21 and 23. The internal DAC registers are edge
triggered and not level triggered. When the LDAC signal is
transitioned from LOW to HIGH, the digital word currently in
the input registers are latched. This double-buffered architec-
ture has been designed so that new data can be entered for
each DAC without disturbing the analog outputs. When the
new data has been entered into the device, both DAC
outputs can be updated simultaneously by the rising edge of
LDAC. Additionally, it allows the input registers to be written
to at any point, then the DAC output voltages can be
synchronously changed via a trigger signal (LDAC).
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to operate
the shift register (the remaining pin should be tied to DGND).
Please refer to Table II for more information.
SERIAL-DATA OUTPUT
The Serial-Data Output pin (SDO) is the internal shift register's
output. For the DAC7632, SDO is a driven output and does
not require an external pull-up. Any number of DAC7632s
can be daisy-chained by connecting the SDO pin of one
device to the SDI pin of the following device in the chain, as
shown in Figure 14.
DAC7632
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SBAS234
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FIGURE 15. Digital Input and Output Timing.
DACSEL
(LSB)
SDI
CLK
CS
LOAD
X
D15
D1
D0
SDI
CLK
LDAC
RST
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
S
t
RSTH
t
RSTL
t
RSSS
t
RSSH
t
CSH
t
S
0.003% FSR
ERROR BAND
0.003% FSR
ERROR BAND
RSTSEL
X
X
X
X
X
QUICK
LOAD
(MSB)
t
LDDD
LDAC
t
LDDH
t
LDDL
t
SDO
SDO
DIGITAL TIMING
Figure 15 and Table III provide detailed timing for the digital
interface of the DAC7632.
DIGITAL INPUT CODING
The DAC7632 input data is in Straight Binary format. The
output voltage is given by Equation 1.
V
V
L
V
H
V
L
N
OUT
REF
REF
REF
=
+
(
)
,
65 536
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
DIGITALLY-PROGRAMMABLE CURRENT SOURCE
The DAC7632 offers a unique set of features that allows a
wide range of flexibility in designing application circuits such
as programmable current sources. The DAC7632 offers both
a differential reference input, as well as an open-loop con-
figuration around the output amplifier. The open-loop con-
figuration around the output amplifier allows a transistor to be
placed within the loop to implement a digitally-program-
mable, unidirectional current source. The availability of a
differential reference allows programmability for both the full-
scale and zero-scale currents. The output current is calcu-
lated as:
I
V
H
V
L
R
V
L R
OUT
REF
REF
SENSE
REF
SENSE
=
+
(
)
,
/
N
65 536
DAC7632
19
SBAS234
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SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t
DS
Data Valid to CLK Rising
10
ns
t
DH
Data Held Valid after CLK Rises
20
ns
t
CH
CLK HIGH
25
ns
t
CL
CLK LOW
25
ns
t
CSS
CS LOW to CLK Rising
15
ns
t
CSH
CLK HIGH to CS Rising
0
ns
t
LD1
LOAD HIGH to CLK Rising
10
ns
t
LD2
CLK Rising to LOAD LOW
30
ns
t
LDRW
LOAD LOW Time
30
ns
t
LDDL
LDAC LOW Time
100
ns
t
LDDH
LDAC HIGH Time
100
ns
t
LDDD
LOAD LOW to LDAC Rising
40
ns
t
RSSS
RESETSEL Valid to RESET HIGH
0
ns
t
RSSH
RESET HIGH to RESETSEL Not Valid
100
ns
t
RSTL
RESET LOW Time
10
ns
t
RSTH
RESET HIGH Time
10
ns
t
SDO
SDO Propogation Delay
10
30
ns
t
S
Settling Time
10
s
TABLE III. Timing Specifications (T
A
= 40
C to +85
C).
FIGURE 16. 4-20mA Digitally-Controlled Current Source.
V
OUT
A
V
OUT
A Sense
V
REF
L Sense
V
REF
L
V
REF
H
V
REF
H Sense
V
OUT
B Sense
V
OUT
B
32
31
30
29
28
27
26
25
DAC7632
1000pF
I
OUT
100
+2.5V
20k
80k
+V
+V
OPA2350
100
2200pF
1000pF
2200pF
V
PROGRAMMED
125
I
OUT
V
PROGRAMMED
125
Figure 16 shows a DAC7632 in a 4-20mA current output
configuration. The output current can be determined by
Equation 3:
I
V
V
N
V
OUT
=
+
2 5
0 5
125
65 536
0 5
125
.
.
,
.
At full-scale, the output current is 16mA, plus the 4mA, for the
zero current. At zero scale the output current is the offset
current of 4mA (0.5V/125
).
DAC7632
20
SBAS234
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PACKAGE DRAWING
MTQF002B JANUARY 1995 REVISED MAY 2000
VF (S-PQFP-G32)
PLASTIC QUAD FLATPACK
4040172/D 04/00
Gage Plane
Seating Plane
1,60 MAX
1,45
1,35
8,80
9,20
SQ
0,05 MIN
0,45
0,75
0,25
0,13 NOM
5,60 TYP
1
32
7,20
6,80
24
25
SQ
8
9
17
16
0,25
0,45
0,10
0
7
M
0,20
0,80
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
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