Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ORDERING INFORMATION(1)
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: VSS = 0V
- ELECTRICAL CHARACTERISTICS: VSS = - 5V
- PIN ASSIGNMENTS
- Terminal Functions
- TYPICAL CHARACTERISTICS: VSS = 0V
- TYPICAL CHARACTERISTICS: VSS = - 5V
- THEORY OF OPERATION
- ANALOG OUTPUTS
- DIGITAL INTERFACE
- 3V TO 5V LOGIC INTERFACE
- CS\ AND CLK INPUTS
- GLITCH SUPPRESSION CIRCUIT
- SERIAL DATA OUTPUT
- DIGITAL TIMING
- DIGITAL INPUT CODING
SBAS263 - NOVEMBER 2003
16 Bit, Quad Voltage Output
Digital to Analog Converter
DAC7654
DAC A
DAC
Register A
Bandgap
Voltage Reference
Input
Register A
Shift
Register
DAC B
DAC
Register B
Input
Register B
DAC C
DAC
Register C
Input
Register C
DAC D
DAC
Register D
Input
Register D
V
OUTA
V
OUTA
Sense 1
V
OUTA
Sense 2
SDI
SDO
Control
Logic
CS
CLOCK
RST
RSTSEL
LDAC
LOAD
A GN D
D GN D
OFSR2A
OFSR1A
V
C C
V
S S
V
DD
D AC 7654
IO V
D D
V
REFL
A and B
V
REFH
A and B
V
REFH
C and D
V
REFL C
and D
V
OUTB
V
OUTB
Sense 1
V
OUTB
Sense 2
OFSR2B
OFSR1B
V
OUTC
V
OUTC
Sense 1
V
OUTC
Sense 2
OFSR2C
OFSR1C
V
OUTD
V
OUTD
Sense 1
V
OUTD
Sense 2
OFSR2D
OFSR1D
V
REFL
V
REFH
FEATURES
D
Low Glitch: 1nV-s (typ)
D
Low Power: 18mW
D
Unipolar or Bipolar Operation
D
Settling Time: 12
s to 0.003%
D
16-Bit Linearity and Monotonicity:
40
C to +85
C
D
Programmable Reset to Mid-Scale or
Zero-Scale
D
Double-Buffered Data Inputs
D
Internal Bandgap Voltage Reference
D
Power-On Reset
D
3V to 5V Logic Interface
APPLICATIONS
D
Process Control
D
Closed-Loop Servo-Control
D
Motor Control
D
Data Acquisition Systems
D
DAC-per-Pin Programmers
DESCRIPTION
The DAC7654 is a 16-bit, quad voltage output,
digital-to-analog converter (DAC) with 16-bit monotonic
performance over the specified temperature range. It
accepts 24-bit serial input data, has double-buffered DAC
input logic (allowing simultaneous update of all DACs),
and provides a serial data output for daisy-chaining
multiple DACs. Programmable asynchronous reset clears
all registers to a mid-scale code of 8000h or to a zero-scale
of 0000h. The DAC7654 can operate from a single +5V
supply or from +5V and 5V supplies.
Low power and small size per DAC make the DAC7654
ideal for automatic test equipment, DAC-per-pin
programmers, data acquisition systems, and closed-loop
servo-control. The DAC7654 is available in an LQFP
package and is specified for operation over the 40
C to
+85
C temperature range.
This device has ESD-CDM sensitivity and special handling precautions must be taken.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
All trademarks are the property of their respective owners.
www.ti.com
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
2
ORDERING INFORMATION
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC7654Y
LQFP-64
PM
-40
C to +85
C
DAC7654Y
DAC7654YT
Tape and Reel, 250
DAC7654Y
LQFP-64
PM
-40
C to +85
C
DAC7654Y
DAC7654YR
Tape and Reel, 1500
DAC7654YB
LQFP-64
PM
-40
C to +85
C
DAC7654YB
DAC7654YBT
Tape and Reel, 250
DAC7654YB
LQFP-64
PM
-40
C to +85
C
DAC7654YB
DAC7654YBR
Tape and Reel, 1500
DAC7654YC
LQFP-64
PM
-40
C to +85
C
DAC7654YC
DAC7654YCT
Tape and Reel, 250
DAC7654YC
LQFP-64
PM
-40
C to +85
C
DAC7654YC
DAC7654YCR
Tape and Reel, 1500
(1) For the most current specification and package information, see the Package Ordering Addendum at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
DAC7654
UNIT
IOVDD, VCC and VDD to VSS
-0.3 to 11
V
IOVDD, VCC and VDD to GND
-0.3 to 5.5
V
Digital Input Voltage to GND
-0.3 to VDD + 0.3
V
Digital Output Voltage to GND
-0.3 to VDD + 0.3
V
ESD-CDM
200
V
Maximum Junction Temperature
+150
C
Operating Temperature Range
-40 to +85
C
Storage Temperature Range
-65 to +125
C
Lead Temperature (soldering, 10s)
+300
C
(1) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
3
ELECTRICAL CHARACTERISTICS: V
SS
= 0V
All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = 0V, unless otherwise noted.
DAC7654Y
DAC7654YB
DAC7654YC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Accuracy
Linearity error
3
4
2
3
[
[
LSB
Linearity match
4
2
[
LSB
Differential linearity error
2
3
1
2
-1
+2
LSB
Monotonicity, TMIN to TMAX
14
15
16
Bit
Unipolar zero error
1
5
[
[
[
[
mV
Unipolar zero error drift
5
10
[
[
[
[
ppm/
C
Full-scale error
6
20
4
12.5
[
[
mV
Full-scale error drift
7
15
[
[
[
[
ppm/
C
Unipolar zero matching
Channel-to-channel matching
3
7
2
5
[
[
mV
Full-Scale matching
Channel-to-channel matching
4
10
2
8
[
[
mV
Power-supply rejection ratio (PSRR)
At full-scale
10
100
[
[
[
[
ppm/V
Analog Output
Voltage output
RL = 10k
0
2.5
[
[
[
[
V
Output current
-1.25
+1.25
[
[
[
[
mA
Maximum load capacitance
No oscillation
500
[
[
pF
Short-circuit current
20
[
[
mA
Short-circuit duration
GND or VCC
Indefinite
[
[
Dynamic Performance
Settling time
To
0.003%, 2.5V output step
12
15
[
[
[
[
s
Channel-to-channel crosstalk
0.5
[
[
LSB
Digital feedthrough
2
[
[
nV-s
Output noise voltage
f = 10kHz
130
[
[
nV/
Hz
DAC glitch
7FFFh to 8000h or
8000h to 7FFFh
1
5
[
[
[
[
nV-s
Digital Input
VIH
0.7
IOVDD
[
[
V
VIL
0.3
IOVDD
[
[
V
IIH
10
[
[
A
IIL
10
[
[
A
Digital Output
VOH
IOH = -0.8mA, IOVDD = 5V
3.6
4.5
[
[
[
[
V
VOL
IOL = 1.6mA, IOVDD = 5V
0.3
0.4
[
[
[
[
V
VOH
IOH = -0.4mA, IOVDD = 3V
2.4
2.6
[
[
[
[
V
VOL
IOL = 0.8mA, IOVDD = 3V
0.3
0.4
[
[
[
[
V
Power Supply
VDD
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
IOVDD
+2.7
+5.0
+5.25
[
[
[
[
[
[
V
VCC
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
VSS
0
0
0
[
[
[
[
[
[
V
ICC
3.5
5
[
[
[
[
mA
IDD
50
[
[
A
I(IOVDD)
50
[
[
A
Power
18
25
[
[
[
mW
Temperature Range
Specified performance
-40
+85
[
[
[
[
C
[
specifications same as the grade to the left
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
4
ELECTRICAL CHARACTERISTICS: V
SS
= -5V
All specifications at TA = TMIN to TMAX, IOVDD = VDD = VCC = +5V, and VSS = -5V, unless otherwise noted.
DAC7654Y
DAC7654YB
DAC7654YC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Accuracy
Linearity error
3
4
2
3
[
[
LSB
Linearity match
4
2
[
LSB
Differential linearity error
2
3
1
2
-1
+2
LSB
Monotonicity, TMIN to TMAX
14
15
16
Bit
Bipolar zero error
1
5
[
[
[
[
mV
Bipolar zero error drift
5
10
[
[
[
[
ppm/
C
Full-scale error
6
20
4
12.5
[
[
mV
Full-scale error drift
7
15
[
[
[
[
ppm/
C
Bipolar zero matching
Channel-to-channel matching
3
7
2
5
[
[
mV
Full-Scale matching
Channel-to-channel matching
4
10
2
8
[
[
mV
Power-supply rejection ratio (PSRR)
At full-scale
10
100
[
[
[
[
ppm/V
Analog Output
Voltage output
RL = 10k
-2.5
+2.5
[
[
[
[
V
Output current
-1.25
+1.25
[
[
[
[
mA
Maximum load capacitance
No oscillation
500
[
[
pF
Short-circuit current
-15, +30
[
[
mA
Short-circuit duration
GND or VCC or VSS
Indefinite
[
[
Dynamic Performance
Settling time
To
0.003%, 5V output step
12
15
[
[
[
[
s
Channel-to-channel crosstalk
0.5
[
[
LSB
Digital feedthrough
2
[
[
nV-s
Output noise voltage
f = 10kHz
200
[
[
nV/
Hz
DAC glitch
7FFFh to 8000h or
8000h to 7FFFh
2
7
[
[
[
[
nV-s
Digital Input
VIH
0.7
IOVDD
[
[
V
VIL
0.3
IOVDD
[
[
V
IIH
10
[
[
A
IIL
10
[
[
A
Digital Output
VOH
IOH = -0.8mA, IOVDD = 5V
3.6
4.5
[
[
[
[
V
VOL
IOL = 1.6mA, IOVDD = 5V
0.3
0.4
[
[
[
[
V
VOH
IOH = -0.4mA, IOVDD = 3V
2.4
2.6
[
[
[
[
V
VOL
IOL = 0.8mA, IOVDD = 3V
0.3
0.4
[
[
[
[
V
Power Supply
VDD
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
IOVDD
+2.7
+5.0
+5.25
[
[
[
[
[
[
V
VCC
+4.75
+5.0
+5.25
[
[
[
[
[
[
V
VSS
-5.25
-5.0
-4.75
[
[
[
[
[
[
V
ICC
4
5.5
[
[
[
[
mA
IDD
50
[
[
A
I(IOVDD)
50
[
[
A
ISS
-3.5
-2.0
[
[
[
[
mA
Power
30
45
[
[
[
mW
Temperature Range
Specified performance
-40
+85
[
[
[
[
C
[
specifications same as the grade to the left
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
5
PIN ASSIGNMENTS
LQFP PACKAGE
(TOP VIEW)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
NC
V
DD
DGND
RSTSEL
RST
LDAC
LOAD
SDI
CLK
CS
SDO
IOV
DD
V
DD
DGND
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
V
OU
T
D
V
OU
T
D
S
ens
e
1
V
OU
T
D
S
ens
e
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
CC
V
OU
T
A
V
OU
T
AS
e
n
s
e
1
V
OU
T
AS
e
n
s
e
2
AG
N
D
NC
NC
NC
NC
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
11
37
36
35
34
33
12
13
14
15
16
DAC7654
Offset D Range 1
Offset D Range 2
Offset C Range 2
Offset C Range 1
V
OUT
C Sense 2
V
OUT
C Sense 1
V
OUT
C
Reference GND
Reference GND
V
OUT
B
V
OUT
B Sense 1
V
OUT
B Sense 2
Offset B Range 1
Offset B Range 2
Offset A Range 2
Offset A Range 1
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
6
Terminal Functions
PIN
NAME
DESCRIPTION
1
NC
No Connection
2
NC
No Connection
3
VSS
Analog 5V power supply or 0V single supply
4
VCC
Analog +5V power supply
5
VOUTA
DAC A output voltage
6
VOUTA
Sense 1
Connect to VOUTA for unipolar mode
7
VOUTA
Sense 2
Connect to VOUTA for bipolar mode
8
AGND
Analog ground
9
NC
No connection
10
NC
No connection
11
NC
No connection
12
NC
No connection
13
NC
No connection
14
NC
No connection
15
NC
No connection
16
NC
No connection
17
DGND
Digital ground
18
VDD
Digital +5V power supply
19
IOVDD
Interface power supply
20
SDO
Serial data output
21
CS
Chip select, active low
22
CLK
Data clock input
23
SDI
Serial data input
24
LOAD
DAC input register load control, active low
25
LDAC
DAC register load control, rising edge triggered
26
RST
Reset, rising edge triggered. Depending on
the state of RSTSEL, the DAC registers are
set to either mid-scale or zero.
27
RSTSEL
Reset select. Determines the action of RST.
If high, an RST command sets the DAC
registers to mid-scale (8000h). If low, an RST
command sets the DAC registers to zero
(0000h).
28
DGND
Digital ground
29
VDD
Digital +5V power supply
30
NC
No connection
31
NC
No connection
32
NC
No connection
33
NC
No connection
34
NC
No connection
35
NC
No connection
PIN
NAME
DESCRIPTION
36
NC
No connection
37
NC
No connection
38
NC
No connection
39
NC
No connection
40
NC
No connection
41
NC
No connection
42
NC
No connection
43
NC
No connection
44
VOUTD
Sense 2
Connect to VOUTD for bipolar mode
45
VOUTD
Sense 1
Connect to VOUTD for unipolar mode
46
VOUTD
DAC D output
47
NC
No connection
48
NC
No connection
49
Offset D
Range 1
Connect to Offset D Range 2 for unipolar
mode
50
Offset D
Range 2
Connect to Offset D Range 1 for unipolar
mode
51
Offset C
Range 2
Connect to Offset C Range 1 for unipolar
mode
52
Offset C
Range 1
Connect to Offset C Range 2 for unipolar
mode
53
VOUTC
Sense 2
Connect to VOUTC for bipolar mode
54
VOUTC
Sense 1
Connect to VOUTC for unipolar mode
55
VOUTC
DAC C output
56
REF GND
Reference ground
57
REF GND
Reference ground
58
VOUTB
DAC B output
59
VOUTB
Sense 1
Connect to VOUTB for unipolar mode
60
VOUTB
Sense 2
Connect to VOUTB for bipolar mode
61
Offset B
Range 1
Connect to Offset B Range 2 for unipolar
mode
62
Offset B
Range 2
Connect to Offset B Range 1 for unipolar
mode
63
Offset A
Range 2
Connect to Offset A Range 1 for unipolar
mode
64
Offset A
Range 1
Connect to Offset A Range 2 for unipolar
mode
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
7
TYPICAL CHARACTERISTICS: V
SS
= 0V
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
+25
5
C
Figure 1
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
_
C)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 2
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
L
E
(
L
SB)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 3
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 4
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
L
E
(
L
SB)
D
L
E
(
L
SB)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
8
TYPICAL CHARACTERISTICS: V
SS
= 0V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
+85
5
C
Figure 5
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
D
L
E
(
L
SB)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 6
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
L
E
(
L
SB)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 7
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
D
L
E
(
L
SB)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 8
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
9
TYPICAL CHARACTERISTICS: V
SS
= 0V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
-40
5
C
Figure 9
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A,
-
40
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
D
L
E
(
L
SB)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 10
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B,
-
40
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 11
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C,
-
40
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 12
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D,
-
40
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
10
TYPICAL CHARACTERISTICS: V
SS
= 0V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
Figure 13
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
CC
(m
A
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
SUPPLY CURRENT vs TEMPERATURE
All DACs at Midscale
No Load
I
CC
Figure 14
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Digital Input Code
0000h
2000h 4000h
6000h
8000h
A000h C000h
E000h FFFFh
SUPPLY CURRENT vs DIGITAL INPUT CODE
I
CC
(m
A
)
All DACs
No Load
I
CC
Figure 15
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
Ze
ro
-
S
c
a
l
e
E
rr
o
r
(m
V
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
ZERO-SCALE ERROR vs TEMPERATURE
DAC A
DAC C
DAC B
DAC D
(Code 0000h)
Figure 16
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
P
o
s
i
t
i
ve
F
u
l
l
-
S
ca
l
e
E
r
r
o
r
(
m
V
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
DAC C
DAC B
DAC D
DAC A
(Code FFFFh)
N
o
i
s
e
V
ol
t
age
(
1
0
0
V/
d
i
v
)
Time (10ms/div)
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
Figure 17
Figure 18
1000
100
10
No
i
s
e
(
n
V
Hz
)
10
100
1k
10k
100k
1M
Frequency (Hz)
OUTPUT NOISE VOLTAGE vs FREQUENCY
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
11
TYPICAL CHARACTERISTICS: V
SS
= 0V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
Figure 19
SETTLING TIME
(0V to +2.5V)
Time (5
s/div)
O
u
tput
V
o
l
t
ag
e
Large Signal: 1.0V/div
Small Signal: 100
V/div
Figure 20
SETTLING TIME
(+2.5V to 39mV)
Time (5
s/div)
O
u
tput
V
o
l
t
ag
e
Large Signal: 1.0V/div
Small Signal: 100
V/div
Figure 21
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
Time (0.5
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
1
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output after
2K, 470pF Low-Pass Filter
Figure 22
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Time (0.5
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
1
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low-Pass Filter
Figure 23
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
Time (1.0
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
2
0
m
V
/
di
v
)
Unfiltered DAC Output
100
Codes
DAC Output After
2K, 470pF Low-Pass Filter
Figure 24
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
Time (1.0
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
2
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low-Pass Filter
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
12
TYPICAL CHARACTERISTICS: V
SS
= 0V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = 0V, representative unit, unless otherwise noted.
Figure 25
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
OU
T
(V
)
0.01
0.1
1
10
100
R
LOAD
(k
)
V
OUT
vs R
LOAD
Sink
Source
Figure 26
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Log
i
c
S
u
p
p
l
y
C
u
r
r
ent
(
m
A
)
0
1
2
3
4
5
Logic Input Level for Digital Inputs (V)
IOVDD SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DIGITAL INPUTS
Typical of One
Digital Input
IOVDD = 5V
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
13
TYPICAL CHARACTERISTICS: V
SS
= -5V
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
+25
5
C
Figure 27
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25
_
C)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 28
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
D
L
E
(
L
SB)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 29
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 30
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +25
_
C)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
D
L
E
(
L
SB)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
14
TYPICAL CHARACTERISTICS: V
SS
= -5V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
+85
5
C
Figure 31
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +85
_
C)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 32
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B, +85
_
C)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 33
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C, +85
_
C)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 34
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D, +85
_
C)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
15
TYPICAL CHARACTERISTICS: V
SS
= -5V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
-40
5
C
Figure 35
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A,
-
40
_
C)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 36
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC B,
-
40
_
C)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 37
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC C,
-
40
_
C)
0000h 2000h 4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
Figure 38
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
LE
(
L
S
B
)
DL
E
(
L
S
B
)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC D,
-
40
_
C)
0000h 2000h
4000h
6000h
8000h
Digital Input Code
A000h C000h E000h FFFFh
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
16
TYPICAL CHARACTERISTICS: V
SS
= -5V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
Figure 39
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
I
CC
(m
A
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
SUPPLY CURRENT vs TEMPERATURE
All DACs at Midscale
No Load
I
CC
I
SS
Figure 40
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
Digital Input Code
0000h
2000h 4000h 6000h
8000h
A000h C000h
E000h FFFFh
SUPPLY CURRENT vs DIGITAL INPUT CODE
I
CC
(m
A
)
All DACs
No Load
I
CC
I
SS
Figure 41
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
B
i
po
l
a
r
Z
er
o
E
r
r
or
(
m
V
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
BIPLOAR ZERO ERROR vs TEMPERATURE
DAC B
DAC C
DAC D
DAC A
(Code 8000h)
Figure 42
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
P
o
s
i
t
i
ve
F
u
l
l
-
S
ca
l
e
E
r
r
o
r
(
m
V
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
DAC B
DAC C
DAC D
DAC A
(Code FFFFh)
Figure 43
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
N
e
g
a
t
i
v
e
F
u
ll
-
S
ca
le
E
r
r
o
r
(
m
V
)
-
40
-
15
10
35
60
85
Temperature (
_
C)
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
DAC B
DAC C
DAC D
DAC A
(Code 0000h)
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
17
TYPICAL CHARACTERISTICS: V
SS
= -5V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
Figure 44
N
o
i
s
e
V
ol
ta
g
e
(
100
V/
d
i
v)
Time (10ms/div)
BROADBAND NOISE
(Code = 8000h, BW = 10kHz)
Figure 45
1000
100
10
No
i
s
e
(
n
V
Hz
)
10
100
1k
10k
100k
1M
Frequency (Hz)
OUTPUT NOISE VOLTAGE vs FREQUENCY
Figure 46
SETTLING TIME
(
-
2.5V to +2.5V)
Time (5
s/div)
O
u
tput
V
o
l
t
ag
e
Large Signal: 1.0V/div
Small Signal: 100
V/div
Figure 47
SETTLING TIME
(+2.5V to
-
2.5V)
Time (5
s/div)
O
u
tput
V
o
l
t
ag
e
Large Signal: 1.0V/div
Small Signal: 100
V/div
Figure 48
MIDSCALE GLITCH PERFORMANCE
CODE 7FFFh to 8000h
Time (0.5
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
1
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output after
2K, 470pF Low-Pass Filter
Figure 49
MIDSCALE GLITCH PERFORMANCE
CODE 8000h to 7FFFh
Time (0.5
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
1
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low-Pass Filter
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
18
TYPICAL CHARACTERISTICS: V
SS
= -5V (continued)
All specifications at TA = 25
C, IOVDD = VDD = VCC = +5V, VSS = -5V, representative unit, unless otherwise noted.
Figure 50
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32750 to 32850
Time (1.0
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
2
0
m
V
/
di
v
)
Unfiltered DAC Output
100
Codes
DAC Output After
2K, 470pF Low-Pass Filter
Figure 51
OVERSHOOT FOR TRANSITION OF 100 CODES
CODE 32850 to 32750
Time (1.0
s/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
2
0
m
V
/
di
v
)
Unfiltered DAC Output
DAC Output After
2K, 470pF Low-Pass Filter
Figure 52
5
4
3
2
1
0
-
1
-
2
-
3
-
4
-
5
V
OU
T
(V
)
0.01
0.1
1
10
100
R
LOAD
(k
)
V
OUT
vs R
LOAD
Sink
Source
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
19
THEORY OF OPERATION
The DAC7654 is a quad voltage output, 16-bit DAC. The
architecture is an R-2R ladder configuration with the three
most significant bits (MSBs) segmented, followed by an
operational amplifier that serves as a buffer. Each DAC
has its own R-2R ladder network, segmented MSBs, and
output op amp, as shown in Figure 53. The minimum
voltage output (zero-scale) and maximum voltage output
(full-scale) are set by the internal voltage references and
the resistors associated with the output operational
amplifier.
The digital input is a 24-bit serial word that contains a 2-bit
address code for selecting one of four DACs, a quick load
bit, five unused bits, and the 16-bit DAC code (MSB first).
The converters can be powered from either a single +5V
supply or a dual
5V supply. The device offers a reset
function that immediately sets all DAC output voltages and
DAC registers to mid-scale (code 8000h) or to zero-scale
(code 0000h). See Figure 54 and Figure 55 for basic
single- and dual-supply operation of the DAC7654.
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
V
REF
H
V
REF
L
V
OUT
V
OUT
S2
V
OUT
S1
OFSR2
OFSR1
13K
13K
12K
13K
11K
100
Figure 53. DAC7654 Architecture
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
20
+3V to +5V
0V to +2.5V
0.1
F
1
F
+
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
NC
V
DD
DGND
RSTSEL
RST
LDAC
LOAD
SDI
CLK
CS
SDO
IOV
DD
V
DD
DGND
NC
NC
NC
Reset DAC Register
Load DAC Registers
Load
Serial Data In
Clock
Chip Select
Serial Data Out
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
V
OUT
D
V
OU
T
D
S
ens
e
1
V
OU
T
D
S
ens
e
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
CC
V
OUT
A
V
OUT
A
S
ens
e
1
V
OUT
A
S
ens
e
2
AG
N
D
NC
NC
NC
NC
NC
NC
NC
NC
48
NC
NC
NC
+5V
NC
NC = No Connection
0V to +2.5V
0V to +2.5V
0V to +2.5V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
47
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
11
37
36
35
34
33
12
13
14
15
16
DAC7654
Single Supply
Offset D Range 1
Offset D Range 2
Offset C Range 2
Offset C Range 1
V
O U T
C Sense 2
V
O U T
C Sense 1
V
O U T
C
Reference GND
Reference GND
V
O U T
B
V
O U T
B Sense 1
V
O U T
B Sense 2
Offset B Range 1
Offset B Range 2
Offset A Range 2
Offset A Range 1
0.1
F
1
F
+
NC
Figure 54. Basic Single-Supply Operation of the DAC7654
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
21
+3V to +5V
-
2.5V to +2.5V
0.1
F
1
F
+
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
NC
V
D D
DGND
RSTSEL
RST
LDAC
LOAD
SDI
CLK
CS
SDO
IOV
D D
V
D D
DGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Reset DAC Register
Load DAC Registers
Load
Serial Data In
Clock
Chip Select
Serial Data Out
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
V
OUT
D
V
OU
T
D
S
ens
e
1
V
OU
T
D
S
ens
e
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
V
CC
V
OUT
A
V
OUT
A
S
ens
e
1
V
OUT
A
S
ens
e
2
AG
N
D
NC
NC
NC
NC
NC
NC
NC
NC
48
NC
-
5V
+5V
NC
NC = No Connection
-
2.5V to +2.5V
-
2.5V to +2.5V
-
2.5V to +2.5V
NC
NC
NC NC NC NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC NC
NC NC
47
46
45
44
43
42
41
40
39
38
1
2
3
4
5
6
7
8
9
10
11
37
36
35
34
33
12
13
14
15
16
DAC7654
Dual Supply
Offset D Range 1
Offset D Range 2
Offset C Range 2
Offset C Range 1
V
OU T
C Sense 2
V
OU T
C Sense 1
V
OU T
C
Reference GND
Reference GND
V
OU T
B
V
OU T
B Sense 1
V
OU T
B Sense 2
Offset B Range 1
Offset B Range 2
Offset A Range 2
Offset A Range 1
0.1
F
1
F
+
0.1
F
1
F
+
Figure 55. Basic Dual-Supply Operation of the DAC7654
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
22
ANALOG OUTPUTS
When V
SS
= 5V (dual-supply operation), the output
amplifier can swing to within 2.25V of the supply rails over
a range of 40
C to +85
C. When V
SS
= 0V (single-supply
operation), and with R
LOAD
also connected to ground, the
output can swing to within 5mV of ground. Care must be
taken when measuring the zero-scale error when
V
SS
= 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (0000h, 0001h, 0002h, etc.) if the output
amplifier has a negative offset.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance are
very important. A 16-bit converter with a 2.5V full-scale
range has a 1LSB value of 38
V. With a load current of
1mA, series wiring and connector resistance of only 40m
(R
W2
) will cause a voltage drop of 40
V, as shown in
Figure 56. To understand what this means in terms of
system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 1/2 m
per square. For
a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6
inches long will result in a voltage drop of 30
V.
The DAC7654 offers a force and sense output
configuration for the high open-loop gain output amplifier.
This feature allows the loop around the output amplifier to
be closed at the load (as shown in Figure 56), thus
ensuring an accurate output voltage.
DIGITAL INTERFACE
Table 1 shows the basic control logic for the DAC7654.
The interface consists of a signal data clock (CLK) input,
serial data in (SDI), DAC input register load control signal
(LOAD), and DAC register load control signal (LDAC). In
addition, a chip select (CS) input is available to enable
serial communication when there are multiple serial
devices. An asynchronous reset (RST) input, by the rising
edge, is provided to simplify startup conditions, periodic
resets, or emergency resets to a known state, depending
on the status of the reset select (RSTSEL) signal.
V
OUT
A Sense1
V
OUT
A
AGND
V
OUT
B Sense1
V
OUT
B
6
5
8
59
58
DAC7654
R
W1
R
W2
V
OUT
R
W1
R
W2
V
OUT
Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7654). R
W
represents wiring resistances.
Table 1. DAC7654 Logic Truth Table
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
INPUT REGISTER
DAC REGISTER
MODE
DAC
L
L
L
H
X
X
L
Write
Hold
Write input
A
L
H
L
H
X
X
L
Write
Hold
Write input
B
H
L
L
H
X
X
L
Write
Hold
Write input
C
H
H
L
H
X
X
L
Write
Hold
Write input
D
X
X
H
H
X
H
Hold
Write
Update
All
X
X
H
H
X
H
H
Hold
Hold
Hold
All
X
X
X
L
X
X
Reset to zero
Reset to zero
Reset to zero
All
X
X
X
H
X
X
Reset to mid-scale
Reset to mid-scale
Reset to mid-scale
All
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
23
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Table 3; also see Figure 58,
page 25). The first two bits select the input register that will
be updated when LOAD goes low. The third bit is a Quick
Load bit; if high, the code in the shift register is loaded into
all of the DAC input registers when the LOAD signal goes
low. If the Quick Load bit is low, the content of shift register
is loaded only to the DAC input register that is addressed.
The Quick Load bit is followed by five unused bits. The last
16 bits (MSB first) are the DAC code.
The internal DAC register is edge triggered and not level
triggered. When the LDAC signal is transitioned from low
to high, the digital word currently in the DAC input register
is latched. The first set of registers (the DAC input
registers) are level triggered via the LOAD signal. This
double-buffered architecture has been designed so that
new data can be entered for each DAC without disturbing
the analog outputs. When the new data has been entered
into the device, all of the DAC outputs can be updated
simultaneously by the rising edge of LDAC. Additionally, it
allows writing to the DAC input registers at any point,
which permits the DAC output voltages to be
synchronously changed via a trigger signal (LDAC).
3V TO 5V LOGIC INTERFACE
All of the digital input and output pins are compatible with
any logic supply voltage between 3V and 5V. Connect the
interface logic supply voltage to the IOV
DD
pin. Note that
the internal digital logic operates from 5V, so the VDD pin
must connect to a 5V supply.
CS AND CLK INPUTS
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. However, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is low when CS rises, the OR gate will
provide a rising edge to the shift register, shifting the internal
data by one additional bit. The result will be incorrect data and
the possible selection of the wrong input register(s). If both
CS and CLK are used, CS should rise only when CLK is high.
If not, then either CS or CLK can be used to operate the shift
register. Table 2 shows more information.
Table 2. Serial Shift Register Truth Table
CS(1)
CLK(1)
LOAD
RST
SERIAL SHIFT REGISTER
H(2)
X(2)
H
H
No change
L(2)
L
H
H
No change
L
(2)
H
H
Advanced one bit
L
H
H
Advanced one bit
H(3)
X
L(4)
H
No change
H(3)
X
H
(5)
No change
(1) CS and CLK are interchangeable.
(2) H = logic high. X = don't care. L = logic low.
= positive logic
transition.
(3) A high value is suggested in order to avoid a false clock from
advancing and changing the shift register.
(4) If data are clocked into the serial register while LOAD is low, the
selected DAC register will change as the shift register bits flow
through A1 and A0. This will corrupt the data in each DAC register
that has been erroneously selected.
(5) Rising edge of RST causes no change in the contents of the serial
shift register.
GLITCH SUPPRESSION CIRCUIT
Figure 21, Figure 22, Figure 48, and Figure 49 show the
typical DAC output when switching between codes 7FFFh
and 8000h. For R-2R ladder DACs, this is potentially the
worst-case glitch condition, since every switch in the DAC
changes state. To minimize the glitch energy at this and
other code pairs with possible high-glitch outputs, an
internal track-and-hold circuit is used to maintain the DAC
ouput voltage at a nearly constant level during the internal
switching interval. This track-and-hold circuit is activated
only when the transition is at, or close to, one of the code
pairs with the high-glitch possibility.
It is advisable to avoid digital transitions within 1
s of the
rising edge of the LDAC signal. These signals can affect
the charge on the track-and-hold capacitor, thus
increasing the glitch energy.
Table 3. 24-Bit Data and Command Word
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A1
A0
Quick
Load
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
24
SERIAL DATA OUTPUT
The serial-data output (SDO) is the internal shift register
output. For the DAC7654, the SDO is a driven output and
does not require an external pull-up. Any number of
DAC7654s can be daisy-chained by connecting the SDO
pin of one device to the SDI pin of the following device in
the chain, as shown in Figure 57.
DIGITAL TIMING
Figure 58 and Table 4 provide detailed timing for the digital
interface of the DAC7654.
DIGITAL INPUT CODING
The DAC7654 input data is in straight binary format. The
output voltage for single-supply operation is given by
Equation 1:
V
OUT
+
2.5
N
65, 536
where N is the digital input code.
This equation does not include the effects of offset
(zero-scale) or gain (full-scale) errors.
The output for the dual supply operation is given by
Equation 2:
V
OUT
+
5
N
65, 536
*
2.5
DAC7654
CLK
SDI
CS
SCK
DIN
CS
SDO
DAC7654
CLK
SDI
CS
SDO
DAC7654
CLK
SDI
CS
SDO
To
Other
Serial
Devices
Figure 57. Daisy-Chaining the DAC7654
(1)
(2)
DAC7654
SBAS263 - NOVEMBER 2003
www.ti.com
25
A1
(LSB)
SDI
CLK
CS
LOAD
A0
D15
D1
D0
SDI
CLK
LDAC
RST
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDRW
t
S
t
RSTH
t
RSTL
t
RSSS
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND
1 LSB
ERROR BAND
RSTSEL
X
X
X
X
X
QUICK
LOAD
(MSB)
t
LDDD
LDAC
t
LDDH
t
LDDL
Figure 58. Digital Input and Output Timing
Table 4. Timing Specifications for Figure 58
SYMBOL
DESCRIPTION
MIN
UNITS
tDS
Data valid to CLK rising
10
ns
tDH
Data held valid after CLK rises
20
ns
tCH
CLK high
25
ns
tCL
CLK low
25
ns
tCSS
CS low to CLK rising
15
ns
tCSH
CLK high to CS rising
0
ns
tLD1
LOAD high to CLK rising
10
ns
tLD2
CLK rising to LOAD low
30
ns
tLDRW
LOAD low time
30
ns
tLDDL
LDAC low time
100
ns
tLDDH
LDAC high time
150
ns
tRSSS
RSTSEL valid to RST high
0
ns
tRSSH
RST high to RSTSEL not valid
100
ns
tRSTL
RST low time
10
ns
tRSTH
RST high time
10
ns
tS
Settling time
10
s
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
DAC7654YBR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YBT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YCR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YCT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YR
ACTIVE
LQFP
PM
64
1500
TBD
CU SNPB
Level-3-240C-168 HR
DAC7654YT
ACTIVE
LQFP
PM
64
250
TBD
CU SNPB
Level-3-240C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Addendum-Page 1
MECHANICAL DATA
MTQF008A JANUARY 1995 REVISED DECEMBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
4040152 / C 11/96
32
17
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
Gage Plane
0,27
33
16
48
1
0,17
49
64
SQ
SQ
10,20
11,80
12,20
9,80
7,50 TYP
1,60 MAX
1,45
1,35
0,08
0,50
M
0,08
0
7
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
IMPORTANT NOTICE
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