1
DAC811
DAC811
Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The DAC811 is a complete, single-chip integrated-
circuit, microprocessor-compatible, 12-bit digital-to-
analog converter. The chip combines a precision volt-
age reference, microcomputer interface logic, and
double-buffered latch, in a 12-bit D/A converter with
a voltage output amplifier. Fast current switches and a
laser-trimmed thin-film resistor network provide a
highly accurate and fast D/A converter.
Microcomputer interfacing is facilitated by a double-
buffered latch. The input latch is divided into three
4-bit nibbles to permit interfacing to 4-, 8-, 12-, or
16-bit buses and to handle right-or left-justified data.
The 12-bit data in the input latches is transferred to the
D/A latch to hold the output value.
Input gating logic is designed so that loading the last
nibble or byte of data can be accomplished simulta-
neously with the transfer of data (previously stored in
adjacent latches) from adjacent input latches to the
D/A latch. This feature avoids spurious analog output
values while using an interface technique that saves
computer instructions.
The DAC811 is laser trimmed at the wafer level and
is specified to
1/4LSB maximum linearity error (B,
K, and S grades) at 25
C and
1/2LSB maximum over
the temperature range. All grades are guaranteed mono-
tonic over the specification temperature range.
The DAC811 is available in six performance grades
and three package types. DAC811J and K are speci-
fied over the temperature ranges of 0
C to +70
C;
DAC811A and B are specified over 25
C to +85
C;
DAC811R and S are specified over 55
C to +125
C.
DAC811J and K are packaged in a reliable 28-pin
plastic DIP or plastic SOIC package, while DAC811A,
B, R and S are available in a 28-pin 0.6" wide dual-
inline hermetically sealed ceramic side-brazed pack-
age (H package).
FEATURES
q
SINGLE INTEGRATED CIRCUIT CHIP
q
MICROCOMPUTER INTERFACE:
DOUBLE-BUFFERED LATCH
q
VOLTAGE OUTPUT:
10V,
5V, +10V
q
MONOTONICITY GUARANTEED OVER
TEMPERATURE
q
1/2LSB MAXIMUM NONLINEARITY OVER
TEMPERATURE
q
GUARANTEED SPECIFICATIONS AT
12V
AND
15V SUPPLIES
q
TTL/5V CMOS-COMPATIBLE LOGIC
INPUTS
1983 Burr-Brown Corporation
PDS-503K
Printed in U.S.A. January, 2000
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
For most current data sheet and other product
information, visit www.burr-brown.com
BPO
V
OUT
D/A Latch
Input Latch
4 MSBs
Input Latch
Input Latch
4 LSBs
12-Bit D/A Converter
Voltage Reference
10V
R
F
S
J
R
F
R
BPO
DAC811
2
DAC811AH, JP, JU
DAC811BH, KP, KU
DAC811RH
DAC811SH
PARAMETER
MIN
TYP
MAX
MIN
TYP MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DIGITAL INPUT
Resolution
12
T
T
T
Bits
Codes
(1)
USB, BOB
T
T
T
Digital Inputs Over Temperature Range
(2)
V
IH
+2
+15
T
T
T
T
T
T
VDC
V
IL
0
+0.8
T
T
T
T
T
T
VDC
I
IH
, V
I
= +2.7V
+10
T
T
T
A
I
IL
, V
I
= +0.4V
20
T
T
T
A
Digital Interface Timing Over Temperature Range
t
WP
, WR Pulse Width
50
T
T
T
ns
t
AW
1, N
X
and LDAC Valid to End of WR
50
T
T
T
ns
t
DW
, Data Valid to End of WR
80
T
T
T
ns
t
DH
, Data Valid Hold Time
0
T
+10
T
ns
ACCURACY
Linearity Error
1/4
1/2
1/8
1/4
1/4
1/2
1/8
1/4
LSB
Differential Linearity Error
1/2
3/4
1/4
1/2
1/2
3/4
1/4
1/2
LSB
Gain Error
(3)
0.1
0.2
T
T
T
T
T
T
%
Offset Error
(3, 4)
0.05
0.15
T
T
T
T
T
T
% of FSR
(5)
Monotonicity
Guaranteed
T
T
T
Power Supply Sensitivity: +V
CC
0.001
0.003
T
T
T
T
T
T
% of FSR/%V
CC
V
CC
0.002
0.006
T
T
T
T
T
T
% of FSR/%V
CC
V
DD
0.0005
0.0015
T
T
T
T
T
T
% of FSR/%V
DD
DRIFT (Over Specification Temperature Range)
Gain
10
30
10
20
15
30
15
30
ppm/
C
Unipolar Offset
5
10
5
7
5
10
5
7
ppm of FSR/
C
Bipolar Zero
5
10
5
7
5
10
5
7
ppm of FSR/
C
Linearity Error Over Temperature Range
1/2
3/4
1/4
1/2
1/2
3/4
1/4
1/2
LSB
Monotonicity Over Temperature Range
Guaranteed
T
T
T
SETTLING TIME
(6)
(to within
0.01% of FSR of Final Value; 2k
load)
For Full Scale Range Change, 20V Range
3
4
T
T
T
T
T
T
s
10V Range
3
4
T
T
T
T
T
T
s
For 1LSB Change at Major Carry
(7)
1
T
T
T
s
Slew Rate
(6)
8
12
T
T
T
T
T
T
V/
s
ANALOG OUTPUT
Voltage Range (
V
CC
= 15V)
(8)
: Unipolar
0 to +10
T
T
T
V
Bipolar
5,
10
T
T
T
V
Output Current
5
T
T
T
mA
Output Impedance (at DC)
0.2
T
T
T
Short Circuit to Common Duration
Indefinite
T
T
T
REFERENCE VOLTAGE
Voltage
+6.2
+6.3
+6.4
T
T
T
T
T
T
T
T
T
V
Source Current Available for External Loads
+2
T
T
T
mA
Temperature Coefficient
10
30
10
20
10
30
10
20
ppm/
C
Short Circuit to Common Duration
Indefinite
T
T
T
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
+11.4
+15
+16.5
T
T
T
T
T
T
T
T
T
VDC
V
CC
11.4
15
16.5
T
T
T
T
T
T
T
T
T
VDC
V
DD
+4.5
+5
+5.5
T
T
T
T
T
T
T
T
T
VDC
Current (no load): +V
CC
+16
+25
T
T
T
T
T
T
mA
V
CC
23
35
T
T
T
T
T
T
mA
V
DD
+8
+15
T
T
T
T
T
T
mA
Potential at DCOM with Respect to ACOM
(9)
0.5
T
T
T
V
Power Dissipation
625
800
T
T
T
T
T
T
mW
TEMPERATURE RANGE
Specification: J, K
0
+70
T
T
T
T
T
T
C
A, B
25
+85
T
T
T
T
T
T
C
R, S
65
+150
T
T
T
T
T
T
C
55
+125
T
T
C
Storage: J, K
60
+100
T
T
T
T
T
T
C
A, B, R, S
65
+150
T
T
T
T
T
T
C
T
Specification same as DAC811AH.
NOTES: (1) USB = unipolar straight binary; BOB = bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim
potentiometer. (4) Error at input code 000
16
for both unipolar and bipolar ranges. (5) FSR means full scale range and is 20V for the
10V range. (6) Maximum
represents the 3
limit. Not 100% tested for this parameter. (7) At the major carry, 7FF
16
to 800
16
and 800
16
to 7FF
16
. (8) Minimum supply voltage required for
10V
output swing is
13.5V. Output swing for
11.4V supplies is at least 8V to +8V. (9) The maximum voltage at which ACOM and DCOM may be separated without
affecting accuracy specifications.
SPECIFICATIONS
At T
A
= +25
C.
V
CC
= 12V or 15V, unless otherwise noted.
3
DAC811
MINIMUM
RELATIVE
DIFFERENTIAL
PACKAGE
SPECIFICATION
ACCURACY
LINEARITY
DRAWING
TEMPERATURE
ORDERING
TRANSPORT
PRODUCT
(LSB)
(LSB)
PACKAGE
NUMBER
RANGE
NUMBER
(1)
MEDIA
DAC811AH
1/2 LSB
3/4
CerDIP-28
149
25
C to +85
C
DAC811AH
Rails
DAC811JP
1/2 LSB
3/4
DIP-28
215
0
C to +70
C
DAC811JP
Rails
DAC811JU
1/2 LSB
3/4
SOIC-28
217
0
C to +70
C
DAC811JU
Rails
"
"
"
"
"
"
DAC811JU/1K
Tape and Reel
DAC811KP
1/4 LSB
1/2
DIP-28
215
0
C to +70
C
DAC811KP
Rails
DAC811KU
1/4 LSB
1/2
SOIC-28
217
0
C to +70
C
DAC811KU
Rails
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of "DAC811JU/1K" will get a single 1000-piece Tape and Reel.
+V
CC ................................................................................................................................
0 to +18V
V
CC
to ACOM .......................................................................... 0 to 18V
V
DD
to DCOM .............................................................................. 0 to +7V
V
DD
to ACOM ......................................................................................
7V
ACOM to DCOM ..................................................................................
7V
Digital Inputs (Pins 214, 1619) to DCOM ...................... 0.4V to +18V
External Voltage Applied to 10V Range Resistor ............................
12V
Ref Out ............................................................. Indefinite Short to ACOM
External Voltage Applied to DAC Output ................................ 5V to +5V
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering, 10s) ............................................... +300
C
Max Junction Temperature ............................................................ +165
C
Thermal Resistance,
J-A
: Plastic DIP and SOIC ....................... 100
C/W
Ceramic DIP .................................................................................. 65
C/W
NOTE: Stresses above those listed above may cause permanent damage to
the device. Exposure to absolute maximum conditions for extended periods
may affect device reliability.
PIN
NAME
FUNCTION
1
+V
DD
Logic supply, +5V.
2
WR
Write, command signal to load latches. Logic low
loads latches.
3
LDAC
Load D/A converter, enables WR to load the D/A
latch. Logic low enables.
4
N
A
Nibble A, enables WR to load input latch A (the
most significant nibble). Logic low enables.
5
N
B
Nibble B, enables WR to load input latch B. Logic
low enables.
6
N
C
Nibble C, enables WR to load input latch C (the
least significant nibble). Logic low enables.
7
D
11
Data bit 12, MSB, positive true.
8
D
10
Data bit 11.
9
D
9
Data bit 10.
10
D
8
Data bit 9.
11
D
7
Data bit 8.
12
D
6
Data bit 7.
13
D
5
Data bit 6.
14
D
4
Data bit 5.
15
DCOM
Digital common, V
DD
supply return.
16
D
0
Data bit 1, LSB.
17
D
1
Data bit 2.
18
D
2
Data bit 3.
19
D
3
Data bit 4.
20
+V
CC
Analog supply input, +15V or +12V.
21
V
CC
Analog supply input, 15V or 12V.
22
Gain Adj
To externally adjust gain.
23
ACOM
Analog common,
V
CC
supply return.
24
V
OUT
D/A converter voltage output.
25
10V Range
Connect to pin 24 for 10V range.
26
SJ
Summing junction of output amplifier.
27
BPO
Bipolar offset. Connect to pin 26 for bipolar
operation.
28
Ref Out
6.3V reference output.
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC811
4
TIMING DIAGRAMS
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
The DAC811 accepts positive-true binary input codes.
DAC811 may be connected by the user for any one of the
following codes: USB (unipolar straight binary), BOB (bi-
polar offset binary) or, using an external inverter on the
MSB line, BTC (binary two's complement). See Table I.
DRIFT
Gain drift is a measure of the change in the full scale range
(FSR) output over the specification temperature range. Drift is
expressed in parts per million per degree centigrade
(ppm/
C). Gain drift is established by testing the full scale
range value (e.g., +FS minus FS) at high temperature, +25
C,
and low temperature, calculating the error with respect to the
+25
C value, and dividing by the temperature change.
Unipolar offset drift is a measure of the change in output
with all 0s on the input over the specification temperature
range. Offset is measured at high temperature, +25
C, and
low temperature. The offset drift is the maximum change in
offset referred to the +25
C value, divided by the tempera-
ture change. It is expressed in parts per million of full scale
range per degree centigrade (ppm of FSR/
C).
Bipolar zero drift is measured at a digital input of 800
16
, the
code that gives zero volts output for bipolar operation.
SETTLING TIME
Settling time is the total time (including slew time) for the
output to settle within an error band around its final value
after a change in input. Three settling times are specified to
0.01% of full scale range (FSR): two for maximum full
scale range changes of 20V and 10V, and one for a 1LSB
change. The 1LSB change is measured at the major carry
(7FF
16
to 800
16
and 800
16
to 7FF
16
), the input transition at
which worst-case settling time occurs.
REFERENCE SUPPLY
DAC811 contains an on-chip 6.3V reference. This voltage
(pin 28) has a tolerance of
0.1V. The reference output may
be used to drive external loads, sourcing at least 2mA. This
current should be constant for best performance of the D/A
converter.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a percent of FSR output change per percent of
change in either the positive, negative, or logic supply
voltages about the nominal voltages. Figure 1 shows typical
power supply rejection versus power supply ripple frequency.
DIGITAL INPUT
ANALOG OUTPUT
USB
BOB
BTC
(1)
Unipolar
Bipolar
Binary
Straight
Offset
Two's
Binary
Binary
Complement
111111111111
+ Full Scale
+ Full Scale
1LSB
100000000000
+ 1/2 Full Scale
Zero
Full Scale
011111111111
+ 1/2 Full Scale 1LSB
1LSB
+ Full Scale
000000000000
Zero
Full Scale
Zero
NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code.
MSB
LSB
TABLE I. Digital Input Codes.
LINEARITY ERROR
Linearity error as used in D/A converter specifications by
Burr-Brown is the deviation of the analog output from a
straight line drawn between the end points (inputs all 1s and
all 0s). The DAC811 linearity error is specified at
1/4LSB
(max) at +25
C for B and K grades, and
1/2LSB (max) for
A, J, and R grades.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the input changes
from one state to the next. Monotonicity requires that DLE
be less than 1LSB over the temperature range of interest.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital inputs. All grades
of DAC811 are monotonic over their specification tempera-
ture range.
Load first rank from Data Bus: LDAC = 1
WR
N
t
AW
t
DW
t
DH
t
WP
A
, N
B
, N
C
DB
11
DB
0
Write Cycle #1
t
SET
WR
1/2LSB
LDAC
t
AW
t
WP
Load second rank from first rank: N
A
, N , N
C
B
= 1
Write Cycle #2
5
DAC811
FIGURE 1. Power Supply Rejection vs Power Supply Ripple
Frequency.
OPERATION
DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 2.
INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into the
D/A register. This double-buffered organization prevents the
generation of spurious analog output values. Each register is
independently addressable.
These input latches are controlled by N
A
, N
B
, N
C
, and WR.
N
A
, N
B
, and N
C
are internally NORed with WR so that the
input latches transmit data when both N
A
(or N
B
, N
C
) and
WR are at logic 0. When either N
A
, (N
B
, N
C
) or WR go to
logic 1, the input data is latched into the input registers and
held until both N
A
(or N
B
, N
C
) and WR go to logic 0.
FIGURE 2. DAC811 Block Diagram.
WR
N
A
N
B
N
C
LDAC
OPERATION
1
X
X
X
X
No operation
0
0
1
1
1
Enables input latch 4MSBs
0
1
0
1
1
Enables input latch 4 middle bits
0
1
1
0
1
Enables input latch 4LSBs
0
1
1
1
0
Loads D/A latch from input latches
0
0
0
0
0
Makes all latches transparent
"X" = Don't care.
TABLE II. DAC813 Interface Logic Truth Table.
GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of offset and gain
adjustments to unipolar and bipolar D/A converter output.
OFFSET ADJUSTMENT
For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output, and adjust the
offset potentiometer for zero output. For bipolar (BOB,
BTC) configurations, apply the digital input code that should
produce the maximum negative output voltage and adjust
the offset potentiometer for minus full scale voltage. Ex-
ample: If the full scale range is connected for 20V, the
maximum negative output voltage is 10V. See Table III for
corresponding codes.
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to
the D/A switches when both LDAC and WR are at logic 0.
When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
All latches are level-triggered. Data present when the con-
trol signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
Table II is a truth table for all latches.
Frequency (Hz)
Percent of FSR per Percent of
Change of Power Supply Voltage
1
0.1
0.01
0.001
0.0001
10
100
1k
10k
100k
+V
CC
V
CC
V
DD
M
1
D0
BPO
SJ
V
OUT
12-Bit D/A Converter
12-Bit D/A Latch
4-Bit Latch, A
27
26
25
24
7
8
9
10
11
12
13
14
19
18
17
16
D11
D8
D7
Reference
2
WR
4
A
5
6
LDAC
3
10V
Range
N
B
N
C
N
D4
D3
ACOM
23
Ref Out
28
R
BPO
R
F
R
F
4-Bit Latch, B
4-Bit Latch, C
MSB
LSB
DAC811
6
12V OPERATION
The DAC811 is fully specified for operation on
12V power
supplies. However, in order for the output to swing to
10V,
the power supplies must be
13.5V or greater. When oper-
ating with
12VB supplies, the output swing should be
restricted to
8V in order to meet specifications.
LOGIC INPUT COMPATIBILITY
The DAC811 digital inputs are TTL, LSTTL, and 54/74HC
CMOS-compatible over the operating range of V
DD
. The
input switching threshold remains at the TLL threshold over
the supply range.
The logic input current over temperature is low enough to
permit driving the DAC811 directly from the outputs of
4000B and 54/74C CMOS devices.
Resistors of 47
should be placed in series with D0 through
D11, WR, N
A
, N
B
, N
C
and LDAC if edges are <10ns or if
the logic input is driven below ground by undershoot.
INSTALLATION
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in Figure 5.
These capacitors (1
F tantalum recommended) should be
located close to the DAC811.
FIGURE 3. Relationship of Offset and Gain Adjustments
for a Unipolar D/A Converter.
FIGURE 4. Relationship of Offset and Gain Adjustments
for a Bipolar D/A Converter.
TABLE III. Digital Input/Analog Output.
ANALOG OUTPUT
DIGITAL INPUT
0 to +10V
5V
10V
111111111111
+9.9976V
+4.9976V
+9.9951V
100000000000
+5V
0V
0V
011111111111
+4.9976V
0.0024V
0.0049V
000000000000
0V
5V
10V
LSB
2.4mV
2.44mV
4.88mV
MSB
LSB
GAIN ADJUSTMENT
For either unipolar or bipolar configurations, apply the
digital input that should give the maximum positive voltage
output. Adjust the gain potentiometer for this positive full
scale voltage. See Table III for positive full scale voltages.
FIGURE 5. Power Supply, Gain, and Offset Potentiometer
Connections.
+ Full Scale
All Bits
Logic 0
1LSB
Range of
Offset Adj.
Offset Adjust Translates the Line
Digital Input
All Bits
Logic 1
Range of
Gain Adjust
Analog Output
Gain Adjust
Rotates the Line
Full Scale Range
+ Full Scale
All Bits
Logic 0
1LSB
Range of
Offset Adjust
Digital Input
All Bits
Logic 1
Analog Output
Full Scale
Range
Gain Adjust
Rotates the Line
Full Scale
MSB on All
Others Off
Bipolar V
Offset
Range of
Gain Adjust
Offset Adj.
Translates
the Line
0.4%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
10k to
100k
DD
V
BPO
V
DD
Summing
Junction
V
ACOM
Gain Adjust
DCOM
+V
CC
V
CC
OUT
1
F
0.0022
F
1
F
3.9M
1
F
V
CC
+V
CC
+V
CC
10k to
100k
V
CC
1M
Connect for
Bipolar Operation
7
DAC811
DAC811 features separate digital and analog power supply
returns to permit optimum connections for low noise and
high speed performance. The analog common (pin 23) and
digital common (pin 15) should be connected together at one
point. Separate returns minimize current flow in low level
signal paths if properly connected. Logic return currents are
not added into the analog signal return path. A
0.5V
difference between ACOM and DCOM is permitted for
specified operation. High frequency noise on DCOM with
respect to ACOM may permit noise to be coupled through to
the analog output; therefore, some caution is required in
applying these common connections.
The Analog Common is the high quality return for the D/A
converter and should be connected directly to the analog
reference point of the system. The load driven by the output
amplifier should be returned to the Analog Common.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and Gain may be trimmed by installing external
Offset and Gain potentiometers. Connect these potentiom-
eters as shown in Figure 5. TCR of the potentiometers
should be 100ppm/
C or less. The 1M
and 3.9M
resis-
tors (20% carbon or better) should be located close to the
DAC811 to prevent noise pickup. If it is not convenient to
use these high value resistors, an equivalent "T" network, as
shown in Figure 6, may be substituted in each case. The
Gain Adjust (pin 22) is a high impedance point and a
0.001
F to 0.01
F ceramic capacitor should be connected
from this pin to Analog Common to reduce noise pickup in
all applications, including those not employing external gain
adjustment. Excessive capacitance on the Gain Adjust or
Offset Adjust pin may affect slew rate and settling time.
FIGURE 6. Equivalent Resistances.
FIGURE 7. Output Amplifier Voltage Range Scaling Circuit.
OUTPUT
DIGITAL
CONNECT
CONNECT
RANGE
INPUT CODES
PIN 25 TO
PIN 27 TO
0 to +10V
USB
24
23
5
BOB or BTC
24
26
10V
BOB or BTC
NC
26
TABLE IV. Output Range Connections.
APPLICATIONS
MICROCOMPUTER BUS INTERFACING
The DAC811 interface logic allows easy interface to micro-
computer bus structures. The control signal WR is derived
from external device select logic and the I/O Write or
Memory Write (depending upon the system design) signals
from the microcomputer.
The latch enable lines N
A
, N
B
, N
C
and LDAC determine
which of the latches are enabled. It is permissible to enable
two or more latches simultaneously, as shown in some of the
following examples.
The double-buffered latch permits data to be loaded into the
input latches of several DAC811s and later strobed into the
D/A latch of all D/As, simultaneously updating all analog
outputs. All the interface schemes shown below use a base
address decoder. If blocks of memory are used, the base
address decoder can be simplified or eliminated altogether.
For instance, if half the memory space is unused, address
line A15 of the microcomputer can be used as the chip select
control.
4-BIT INTERFACE
An interface to a 4-bit microcomputer is shown in Figure 8.
Each DAC811 occupies four address locations. A 74LS139
provides the two-to-four decoder and selects it with the base
address. Memory Write (WR) of the microcomputer is
connected directly to the WR pin of the DAC811. An 8205
decoder is an alternative to the 74LS139.
OUTPUT RANGE CONNECTIONS
Internal scaling resistors provided in the DAC811 may be
connected to produce bipolar output voltage ranges of
10V
and
5V or a unipolar output voltage range of 0 to +10V.
The 20V range (
10V bipolar range) is internally connected.
Refer to Figure 7. Connections for the output ranges are
listed in Table IV.
1M
3.9M
100k
100k
12k
10k
180k
180k
4.26k
5.36k
24
V
OUT
23
Analog Common
From D/A
Converter
From Voltage
Reference
4.26k
25
10V Range
26
Summing Junction
27
Bipolar Offset
DAC811
8
FIGURE 10. Right-Justified Data Bus Interface.
FIGURE 11. Left-Justified Data Bus Interface.
8-BIT INTERFACE
The control logic of DAC811 permits interfacing to right-
justified data formats, as illustrated in Figure 9. When a
12-bit D/A converter is loaded from an 8-bit bus, two bytes
of data are required. Figures 10 and 11 show an addressing
scheme for right-justified and left-justified data respectively.
The base address is decoded from the high-order address
bits. A
0
and A
1
address the appropriate latches. Note that
adjacent addresses are used. For the right-justified case,
X10
16
loads the 8LSBs, and X01
16
loads the 4MSBs and
simultaneously transfers input latch data to the D/A latch.
Addresses X00
16
and X11
16
are not used.
Left-justified data is handled in a similar manner, shown in
Figure 11. The DAC811 still occupies two adjacent loca-
tions in the microcomputer's memory map.
FIGURE 8. Addressing and Control for 4-Bit Microcom-
puter Interface.
FIGURE 9. 12-Bit Data Format for 8-Bit Systems.
D0
D4
D8
D1
D5
D9
D2
D6
D10
D3
D7
D11
16
14
10
17
13
9
18
12
8
19
11
7
DB0
DB1
DB2
DB3
WR
A
A
1
0
Microcomputer
DAC811
Base
Address
Decoder
A
A
N
2
2
3
4
5
6
WR
LDAC
N
N
N
1/2
74LS139
A
B
C
7
6
5
4
1
3
2
CS
(Chip
Select)
A
A
1
0
EN
Y
Y
Y
Y
3
2
1
0
X
X
X
X
D11 D10
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
a. Right-Justified
D11 D10
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
b. Left-Justified
X
X
X
X
D0
D8
D1
D9
D2
D10
D3
D11
D4
D5
D6
D7
16
10
17
9
18
8
19
7
14
13
12
11
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
WR
A
A
1
0
Microcomputer
DAC811
Base
Address
Decoder
A
A
15
2
2
3
4
5
6
WR
LDAC
N
N
N
A
B
C
CS
D4
D5
D6
D7
D8
D0
D9
D1
D10
D2
D11
D3
14
13
12
11
10
16
9
17
8
18
7
19
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
WR
A
A
1
0
Microcomputer
DAC811
Base
Address
Decoder
A
A
15
2
2
3
4
5
6
WR
LDAC
N
N
N
A
B
C
CS
9
DAC811
INTERFACING MULTIPLE DAC811s
IN 8-BIT SYSTEMS
Many applications, such as automatic test systems, require
that the outputs of several D/A converters be updated simul-
taneously. The interface shown in Figure 12 uses a 74LS138
decoder to decode a set of eight adjacent addresses, to load
the input latches of four DAC811s. The example shows a
right-justified data format.
A ninth address using A
3
causes all DAC811s to be updated
simultaneously. If a particular DAC811 is always loaded
last--for instance, D/A #4--A
3
is not needed, thus saving
ADDRESS BUS
A3
A2
A1
A0
OPERATION
0
0
0
0
Load 8 LSB D/A #1
0
0
0
1
Load 4 MSB D/A #1
0
0
1
0
Load 8 MSB D/A #2
0
0
1
1
Load 4 MSB D/A #2
0
1
0
0
Load 8 MSB D/A #3
0
1
0
1
Load 4 MSB D/A #3
0
1
1
0
Load 8 MSB D/A #4
0
1
1
1
Load 4 MSB D/A #4
1
X
X
X
Load D/A Latch--All D/A
FIGURE 12. Interfacing Multiple DAC811s to an 8-Bit Bus.
eight address spaces for other uses. Incorporate A
3
into the
base address decoder, remove the inverter, connect the
common LDAC line to N
C
of D/A #4, and connect D1 of the
74LS138 to +5V.
12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application, the input latch enable lines, N
A
, N
B
and
N
C,
are tied low, causing the latches to be transparent. The
D/A latch, and therefore DAC811, is selected by the address
decoder and strobed by WR.
Base
Address
Decoder
WR
A
A
15
4
A
A
A
2
1
0
Microcomputer
A
3
74LS138
C
B
A
G
G
G
2A
2B
1
WR
LDAC
N
N
N
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
3
2
1
4
6
5
CS
DAC811
(4)
C
B
A
WR
LDAC
N
N
N
DAC811
(1)
C
B
A
WR
LDAC
N
N
N
DAC811
(2)
C
B
A
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